Stacked Semiconductor Chip Support Structure for Void-Free TSV Packaging
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently stacking multiple semiconductor chips while maintaining consistent spacing and preventing voids, which can affect reliability and heat dissipation.
Innovation Solution
A semiconductor package design featuring support structures with metal support posts and insulating adhesive layers to maintain consistent spacing between stacked semiconductor chips, ensuring uniform adhesion and effective heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked closely together to improve integration density, then productivity and space utilization are improved, but manufacturing precision and reliability deteriorate due to difficulty in maintaining consistent spacing and preventing voids
Solution Approach 1:
The patent introduces support structures as intermediary elements between stacked semiconductor chips. These support structures include spacing portions that maintain consistent spacing between adjacent chips, and connection portions that form conductive paths. This intermediary structure resolves the contradiction by enabling close stacking while preserving manufacturing precision through the standardized spacing portions.
Solution Approach 2:
The patent changes the structural parameters by introducing support structures with specific geometric configurations (spacing portions and connection portions). The spacing portions have controlled dimensions that define the spacing between chips, transforming the manufacturing process from direct chip-to-chip contact to a controlled multi-component assembly, thereby improving spacing consistency.
2Reliability
If support structures are added to maintain consistent spacing between chips, then manufacturing precision and reliability are improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the support structures: mechanical spacing (spacing portions), electrical connection (connection portions with conductive paths), and structural support. By combining these functions into a single integrated component rather than using separate elements for each function, the patent improves reliability while minimizing the increase in device complexity.
Solution Approach 2:
The support structures serve multiple purposes simultaneously: they maintain spacing between chips, provide mechanical support, establish electrical connections through conductive paths, and prevent void formation. This multi-functionality reduces the need for additional separate components, thereby improving reliability without proportionally increasing device complexity.
3Productivity
If chips are stacked with minimal spacing to improve integration density, then productivity is improved, but heat dissipation deteriorates due to reduced thermal management space
Solution Approach 1:
The support structures act as thermal intermediaries between stacked chips. The connection portions with conductive paths provide thermal conduction pathways that facilitate heat dissipation, while the spacing portions maintain minimal but sufficient spacing for thermal management. This intermediary structure enables high stacking density while preserving heat dissipation capability.
Solution Approach 2:
The support structures appear to be composed of materials with appropriate thermal conductivity properties to facilitate heat dissipation. The combination of spacing portions (for thermal management space) and connection portions (for thermal conduction) creates a composite structure that simultaneously achieves high stacking density and effective heat dissipation.
Data Source
AI summary
A semiconductor package including a first semiconductor chip; second semiconductor chips sequentially stacked on the first semiconductor chip; a front connection pad on a lower surface of each of the second semiconductor chips; a rear connection pad attached to an upper surface of each of the first semiconductor chip and the second semiconductor chips; a chip connection terminal between the front connection pad and the rear connection pad; and a support structure between the first semiconductor chip and one of the second semiconductor chips and between adjacent ones of the second semiconductor chips, the support structure being spaced apart from the front connection pad, the rear connection pad, and the chip connection terminal, having a vertical height greater than a vertical height of the chip connection terminal, and including a metal.