Stacked Semiconductor Chip Electrode Layout for Symmetric Interconnects
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently stacking semiconductor chips while maintaining effective electrical connections and symmetry in through-electrodes and shared electrodes, which are crucial for high-performance and high-capacity semiconductor devices.
Innovation Solution
The semiconductor package design includes symmetrically arranged through-electrodes and shared electrodes relative to intersecting axes, allowing for vertical stacking of semiconductor chips with overlapping connections, and uses a protective layer for insulation and connection paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-electrodes and shared electrodes are arranged symmetrically in stacked semiconductor chips, then electrical connectivity and performance are improved, but manufacturing precision requirements increase
Solution Approach 1:
The electrode system is segmented into two distinct types: through-electrodes that penetrate the semiconductor chip and shared electrodes that are spaced apart and electrically connected to the through-electrodes. This segmentation allows each electrode type to have optimized functions while maintaining overall symmetry, reducing the precision burden on any single electrode while preserving electrical connectivity.
Solution Approach 2:
While maintaining overall symmetrical arrangement for performance, the patent introduces asymmetry in the spacing and configuration of shared electrodes relative to through-electrodes. The shared electrodes are spaced apart from through-electrodes in a direction intersecting the arrangement direction, creating an asymmetric local pattern that balances manufacturing feasibility with electrical performance requirements.
2Productivity
If semiconductor chips are stacked vertically with overlapping connections, then device capacity and performance increase, but structural complexity increases
Solution Approach 1:
Multiple semiconductor chips are stacked vertically in a nested configuration, with each chip containing through-electrodes and shared electrodes that interconnect across chip boundaries. The overlapping arrangement of electrodes between adjacent chips creates a nested interconnection structure that increases device capacity while organizing complexity in a hierarchical manner.
Solution Approach 2:
The patent transitions from planar electrode arrangements to three-dimensional stacked configurations. Through-electrodes extend vertically through multiple chip layers, and shared electrodes are positioned in intersecting directions, utilizing the vertical dimension to increase connectivity without proportionally increasing planar complexity.
3Reliability
If shared electrodes are spaced apart from through-electrodes in intersecting directions, then electrical connection reliability improves, but manufacturing difficulty increases
Solution Approach 1:
The patent applies different spatial configurations to different electrode types based on their functional requirements. Through-electrodes are arranged in a first direction for primary signal transmission, while shared electrodes are spaced apart in a second direction intersecting the first direction for redundant connectivity. This local optimization of electrode quality improves electrical connection reliability while keeping fabrication processes manageable through clear directional guidance.
Data Source
AI summary
A semiconductor package includes: a first semiconductor chip including a plurality of first through-electrodes and a plurality of first shared electrodes, wherein the first through-electrodes are arranged in a first direction, wherein the plurality of first shared electrodes are spaced apart from the plurality of first through-electrodes in a second direction, intersecting the first direction, and are electrically connected to the plurality of first through-electrodes, respectively; and a second semiconductor chip including a plurality of second through-electrodes and a plurality of second shared electrodes, wherein the plurality of second through-electrodes are disposed on the first semiconductor chip and are arranged in the first direction, wherein the plurality of second shared electrodes are spaced apart from the plurality of second through-electrodes in the second direction and are electrically connected to the plurality of second through-electrodes, respectively.