Stacked Chip Layout With Through-Hole Test Terminal Access
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Solution Overview
Problem
There is a need for a technology that can suppress the increase in size of electronic devices (semiconductor apparatuses) while integrating a test terminal for evaluating electrical characteristics, particularly in devices formed by bonding surfaces of chips with semiconductor elements.
Innovation Solution
The solution involves integrating a first chip with a test terminal and a second chip, where the first chip has a smaller projected area than the second chip, and both chips are arranged such that the first chip is included within the second chip in plan view. This configuration allows for the test terminal to be accessed through a through hole without increasing the size of the electronic device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a test terminal is integrated into an electronic device formed by bonding surfaces of chips with semiconductor elements, then electrical characteristic evaluation capability is improved, but device size increases
Solution Approach 1:
The first chip containing the test terminal is nested within the footprint of the second chip. The first chip is positioned on the first main surface of the second chip such that its projected area is completely included within the projected area of the second chip in plan view, allowing the test terminal to be accessed through a through hole without increasing the overall device size.
Solution Approach 2:
The test terminal is accessed through a through hole that penetrates from the second main surface of the second chip to the first main surface, allowing electrical characteristic evaluation without adding lateral dimensions. This vertical dimension approach enables testing while maintaining a compact footprint.
2Area of stationary object
If the first chip with test terminal is made smaller to fit within the second chip, then device size is reduced, but manufacturing complexity increases
Solution Approach 1:
The first chip is designed and manufactured with predetermined dimensions that ensure its projected area is smaller than the second chip, and its position is pre-determined to be within the second chip's footprint. This preliminary design consideration simplifies the subsequent bonding process by eliminating complex real-time alignment adjustments.
Solution Approach 2:
The first chip is designed with an asymmetric size relationship to the second chip, where the first chip's dimensions are specifically smaller to allow complete inclusion within the second chip's projected area. This asymmetric design provides manufacturing tolerance and simplifies alignment requirements.
Data Source
AI summary
A method for manufacturing an electronic device includes a first chip preparing step, a second chip preparing step, and a fixing step. The first chip preparing step is a step of preparing a first chip in which a first semiconductor element, a first insulating layer, a first wiring layer, and a first connection electrode are provided on a side of a first main surface, and a terminal electrically connected to the first wiring layer is exposed to a side opposite to the first main surface. The second chip preparing step is a step of preparing a second chip in which a second semiconductor element, a second insulating layer, a second wiring layer, and a second connection electrode are provided on a side of a second main surface of a second substrate. The fixing step is a step of fixing the first chip and the second chip.