Stacked Semiconductor Package Thermal Path Around Narrower Chip
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Solution Overview
Problem
As semiconductor chips become more miniaturized and integrated, effective heat dissipation systems are required to manage the heat generated by these packages efficiently.
Innovation Solution
A semiconductor package design incorporating a first interconnection structure with a first semiconductor chip, a second semiconductor chip of smaller width, and a heat dissipation structure surrounding the second chip with higher thermal conductivity than silicon, along with an encapsulant and a second interconnection structure, to enhance heat dissipation without increasing the package's area or thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are miniaturized and integrated to increase degree of integration, then productivity and device functionality are improved, but heat dissipation becomes more difficult and heat accumulation increases
Solution Approach 1:
The patent introduces a heat dissipation structure that extends in the vertical dimension (thickness direction) rather than only in the horizontal plane. The heat dissipation structure includes a first portion covering the upper surface of the first semiconductor chip and a second portion extending downward to cover the lower surface of the first semiconductor chip, creating a three-dimensional heat dissipation pathway that resolves the contradiction by adding spatial dimensionality to heat dissipation.
Solution Approach 2:
The heat dissipation structure acts as an intermediary element between the semiconductor chips and the external environment. It includes a heat dissipation pad electrically connected to the semiconductor chip through an adhesive layer, and this heat dissipation pad is in turn connected to a heat dissipation structure with high thermal conductivity material, creating an intermediary heat transfer pathway that effectively manages heat from miniaturized integrated chips.
2Temperature
If heat dissipation area is increased to improve heat dissipation characteristics, then temperature control is improved, but package area and thickness increase
Solution Approach 1:
The heat dissipation structure utilizes the vertical dimension by extending heat dissipation portions both upward from and downward to the semiconductor chip. The first portion covers the upper surface while the second portion extends downward to cover the lower surface, effectively doubling the heat dissipation area in the vertical direction without increasing the horizontal package footprint, thus resolving the contradiction between heat dissipation area and package volume.
Solution Approach 2:
The heat dissipation structure is nested within the existing package structure. The heat dissipation pad is embedded in the adhesive layer between the semiconductor chip and the interconnection structure, and the heat dissipation portions are integrated into the encapsulant structure. This nesting approach increases heat dissipation area without adding external volume to the package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively radiates heat generated by the semiconductor chips over a larger area externally, improving heat dissipation characteristics while maintaining the package's compact size.
Implementation Method 1
a heat dissipation structure surrounding side surfaces of the second semiconductor chip, the heat dissipation structure on an upper surface of the first semiconductor chip and including a material having higher thermal conductivity than a thermal conductivity of silicon
Data Source
AI summary
A manufacturing method includes: forming a stacked chip structure, wherein forming the stacked chip structure includes: attaching a semiconductor wafer for first semiconductor chips onto a carrier and attaching second semiconductor chips onto the semiconductor wafer, forming a first heat dissipation pattern on an upper surface of the semiconductor wafer and side surfaces of the second semiconductor chips, and cutting the first heat dissipation pattern and the semiconductor wafer to separate the semiconductor wafer into the first semiconductor chips; mounting the stacked chip structure including at least one of the first semiconductor chips and at least one of the second semiconductor chips on a first interconnection structure; and forming a second heat dissipation pattern on the first interconnection structure.