Stacked Semiconductor Chip Through Electrode Parasitic Reduction
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Solution Overview
Problem
In semiconductor devices with stacked chips, parasitic capacitance and inductance of metal wires affect high-speed signal transmission, leading to voltage drops and potential malfunctions due to increased internal resistance and voltage differences across the chips.
Innovation Solution
The semiconductor device employs through electrodes and micro-bumps for electrical connections between chips, with specific contact pad and plug configurations that reduce internal resistance and maintain voltage consistency, enabling high-speed signal transmission and integration of memory cell arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wires are used to electrically connect semiconductor chips to interconnections on the base substrate, then electrical connection between chips and external circuits is achieved, but parasitic capacitance and inductance affect high-speed signal transmission
Solution Approach 1:
The patent extracts and eliminates the problematic metal wire interconnections by directly mounting semiconductor chips onto a leadless substrate. This removes the parasitic capacitance and inductance sources from the signal path, resolving the contradiction between achieving electrical connection and avoiding harmful parasitic effects.
Solution Approach 2:
The patent introduces a leadless substrate as an intermediary between the semiconductor chips and external circuits. This substrate provides electrical connections without the parasitic effects of traditional metal wire interconnections, mediating the connection while maintaining signal integrity for high-speed transmission.
2Reliability
If semiconductor chips are stacked on a base substrate with metal wire connections, then electrical connectivity is achieved, but internal resistance increases and voltage differences occur across chips
Solution Approach 1:
The patent removes the complex metal wire interconnection network that causes voltage drops and internal resistance issues. By directly connecting chips to the leadless substrate, the problematic intermediate connection layer is extracted, resulting in improved voltage consistency across all chips.
3Reliability
If through electrodes and contact pads are configured to reduce internal resistance, then voltage consistency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates contact pads and through electrodes directly into the substrate fabrication process before chip mounting. This preliminary integration of electrical connection structures simplifies subsequent assembly steps and reduces manufacturing complexity while achieving the desired voltage consistency.
Data Source
AI summary
A semiconductor device includes a base member and semiconductor chips stacked on the base member. The semiconductor chips include a first semiconductor chip and a second semiconductor chip adjacent to the first semiconductor chip. The first semiconductor chip includes a semiconductor substrate, a functional layer and through electrodes. The through electrodes extend from the back surface to the front surface of the semiconductor substrate, and are electrically connected to the functional layer on the front surface. The second semiconductor chip is electrically connected to the first semiconductor chip through connection members connected to the through electrodes. The functional layer includes first and second contact pads. The second contact pad is positioned at a level between the semiconductor substrate and the first contact pad. The through electrodes include a first through electrode connected to the first contact pad and a second through electrode connected to the second contact pad.