Stacked-Chip Through-Via Layout for Smaller Package Footprint
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Solution Overview
Problem
The challenge is to reduce the package size of stacked-chip packages while maintaining performance, as the size of individual chips increases, leading to larger package sizes.
Innovation Solution
A stacked-chip package configuration where a second chip is stacked on a first chip without a bonding layer in the vertical direction, with both chips sharing a peripheral circuit region and utilizing through vias for electrical connections, allowing for a compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the first chip or the second chip is increased to increase performance or capacity, then the performance or capacity is improved, but the package size increases
Solution Approach 1:
The patent merges the peripheral circuit regions of the first and second chips into a single shared region. The first peripheral circuit region and the second peripheral circuit region are positioned to overlap when the chips are stacked, forming a common peripheral circuit area that serves both chips. This eliminates the need for separate peripheral circuit regions for each chip, thereby reducing the overall package size while maintaining the performance and capacity of both chips.
2Reliability
If a bonding layer is added between the first chip and the second chip to ensure reliable connection, then the connection reliability is improved, but the package size increases
Solution Approach 1:
The patent extracts and eliminates the bonding layer from the stacked-chip structure. By directly bonding the first chip and the second chip together without an intermediate bonding layer, the design achieves reliable electrical and mechanical connections while minimizing the vertical height of the package. The direct bonding approach maintains connection reliability by ensuring intimate contact between the chips, while simultaneously reducing the overall package dimensions.
3Adaptability or versatility
If separate peripheral circuit regions are provided for the first chip and the second chip, then the functionality is improved, but the chip size and package size increase
Solution Approach 1:
The patent implements a universal peripheral circuit region that serves multiple functions for both the first chip and the second chip. The shared peripheral circuit area contains circuit elements that can be accessed and utilized by both chips, allowing a single region to perform the peripheral functions that would traditionally require separate dedicated regions for each chip. This multi-functional approach maintains the necessary functionality while significantly reducing the overall area required.
Data Source
AI summary
A stacked-chip package of the inventive concepts includes a first chip and a second chip stacked on the first chip. The first chip may include a first cell array region, a first core circuit region including a first core terminal, and a first peripheral circuit region including a plurality of first peripheral circuit terminals. The second chip may include a second cell array region on the first cell array region, a second core circuit region on the first core circuit region and including a second core terminal, and a through via on the first peripheral circuit region and connected to at least one first peripheral circuit terminal of the plurality of first peripheral circuit terminals.