Stacked-Chip Trench Capacitors for High Density in Small Footprints
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Solution Overview
Problem
The integration of capacitors in integrated circuits (ICs) faces challenges in maximizing performance while minimizing footprint, as increasing capacitor density often requires more chip area, which could be used for other devices or functionalities.
Innovation Solution
A structure comprising two stacked chips with a trench capacitor that extends through the second chip, the bonding interface, and at least partially into the first chip, allowing for high capacitance density while conserving chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more capacitors are integrated into ICs to increase performance, then capacitor density is improved, but chip footprint area increases
Solution Approach 1:
The patent transitions from planar capacitor integration to three-dimensional stacked chip architecture. Capacitors are formed vertically through multiple stacked chips with trench structures extending through bonding interfaces, utilizing the vertical dimension to increase capacitor density without expanding chip footprint area.
Solution Approach 2:
The patent implements nested capacitor structures where trench capacitors are formed within stacked chips. The capacitor trenches are nested within the vertical stack, with conductive plugs and dielectric layers nested within the trench structures, maximizing space utilization and capacitance within a compact footprint.
2Quantity of substance
If capacitor integration is increased to improve performance, then capacitance value is improved, but device complexity increases
Solution Approach 1:
The patent divides the capacitor structure into segmented components distributed across multiple stacked chips. Each chip contains portions of the capacitor structure (trenches, dielectric layers, conductive plugs), and the complete capacitor function is achieved through the stacked assembly, allowing complex capacitance values to be built from simpler modular units.
Data Source
AI summary
A structure including a first chip and a second chip stacked over and bonded to the first chip at a bonding interface is provided. The first and second chips form a device stack. The first chip includes a first dielectric and first interconnects arranged in the first dielectric. The second chip includes a second dielectric over the first dielectric and second interconnects arranged in the second dielectric. A trench capacitor is arranged in the device stack. The trench capacitor extends through the second chip, the bonding interface and at least partially into the first chip.