Stacked Chip Package Conductive Pillars to Avoid TSV Misalignment
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Solution Overview
Problem
Existing chip package structures face challenges in efficiently increasing storage capacity while maintaining a standard package size and reducing production costs, particularly due to complex manufacturing processes and alignment issues during semiconductor stacking.
Innovation Solution
A chip package structure with a stack of semiconductor structures featuring conductive pillars that penetrate through dielectric blocks, allowing for simplified fabrication and improved yield by integrating conductive pillars within vias formed during the stacking process, eliminating the need for separate TSV formation and reducing misalignment risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate TSV formation process is used, then connection reliability is improved, but manufacturing complexity and production cost increase
Solution Approach 1:
The patent merges the TSV formation process with the via formation process by using the same etching steps and filling processes. The via structure is extended to penetrate through the bonding interface, eliminating the need for separate TSV formation while maintaining connection reliability through integrated process control.
Solution Approach 2:
The via structure serves multiple functions: it provides electrical connection within the semiconductor structure, penetrates through the bonding interface to connect stacked chips, and eliminates the need for separate TSV formation. This multi-functional design reduces manufacturing complexity while maintaining connection reliability.
2Productivity
If conventional stacking process is used, then chip stacking is achieved, but alignment misalignment occurs between vias and TSVs
Solution Approach 1:
By merging the via and TSV into a single continuous structure that penetrates through the bonding interface, the patent eliminates the alignment interface between via and TSV. This removes the source of alignment errors and ensures precise electrical connection between stacked chips.
Solution Approach 2:
The via structure is designed from the beginning to extend through the bonding interface, so that when chips are stacked, the electrical connection is already pre-established. This preliminary design prevents alignment misalignment issues that would otherwise occur during the stacking process.
3Reliability
If multiple separate processes are used for via and TSV formation, then connection quality is improved, but production efficiency decreases
Solution Approach 1:
The patent combines via formation and TSV formation into a single integrated process sequence. The same etching and filling operations create both structures, reducing the number of process steps while maintaining connection quality through consistent process parameters applied to the entire via-TSV structure.
Solution Approach 2:
The integrated via structure performs multiple connection functions simultaneously, allowing a single process sequence to achieve what previously required multiple separate processes. This multi-functional approach improves production efficiency without compromising connection quality.
Data Source
AI summary
The present disclosure provides a chip package structure and a fabrication method thereof, a memory system, and an electronic apparatus, and relates to the field of chip package technology. The chip package structure includes a stack structure and at least one first conductive pillar. The stack structure includes a plurality of semiconductor structures that are stacked. The stack structure includes a first surface and a second surface that are opposite in a stacking direction. The first conductive pillar extends along the stacking direction from the first surface of the stack structure, penetrates through at least one of the semiconductor structures, and is connected to one of the semiconductor structures. The above-mentioned chip package structure may be applied in a memory system to realize read and write operations of data.