Stacked-Chip TSV Structure Without Additional Conductive Bumps
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Solution Overview
Problem
Conventional through silicon via (TSV) technology requires additional conductive structures, such as solder balls, to establish electrical connections between chips, complicating the semiconductor structure and manufacturing process.
Innovation Solution
The method involves forming TSVs that penetrate through the second chip and a part of the first chip, with a conductive layer in the TSV, allowing for electrical connection between the metal layers of the two chips without additional conductive structures. This simplifies the semiconductor structure and process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional conductive structures (such as solder balls) are used to establish electrical connections between chips, then electrical connection reliability is improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent merges the TSV structure with the inter-chip connection function by extending the TSV through the bonding interface. The conductive layer within the TSV continuously connects metal layers across both chips, eliminating the need for separate solder balls or conductive bumps. This integration of connection pathways into the TSV structure itself reduces device complexity while maintaining electrical connection reliability.
2Reliability
If additional conductive structures (such as solder balls) are used to establish electrical connections between chips, then electrical connection reliability is improved, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process merges TSV formation with inter-chip connection creation. The same etching, insulating layer deposition, and conductive layer formation steps that create TSVs also establish the continuous conductive pathways through the bonding interface. This eliminates separate manufacturing steps for adding solder balls or conductive bumps, thereby simplifying the overall manufacturing process while ensuring reliable electrical connections.
Solution Approach 2:
The patent performs preliminary action by forming the conductive layer in the TSV before the bonding process. The TSV is prepared with the conductive layer in advance, so that when chips are bonded together, the conductive pathways are already established and ready to connect metal layers across the interface. This preliminary preparation eliminates the need for post-bonding steps to add conductive structures.
3Device complexity
If TSV penetrates through both chips to enable direct electrical connection, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies the nesting principle by placing the TSV structure within the bonding interface region. The TSV extends through the bonding layer and aligns with metal layers in both chips, creating a nested configuration where the conductive pathway is embedded within the bonded structure. This nesting approach allows the TSV to serve dual purposes (internal connection and inter-chip connection) while managing alignment requirements through the bonding process.
Data Source
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AI summary
The present application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a stacked structure, the stacked structure includes a first chip and a second chip; forming a through silicon via (TSV) in the stacked structure, the TSV includes a first part and a second part communicating with the first part, a sidewall of the first part is a vertical sidewall, and a sidewall of the second part is an inclined sidewall; forming an insulating layer on the sidewall of the first part; and forming a conductive layer in the TSV. By forming the TSV penetrating through the second chip and a part of the first chip, and forming the conductive layer in the TSV, the semiconductor structure and the manufacturing method thereof in the present application can implement electrical connection between the metal layers in the first chip and the second chip without an additional conductive structure, and thus the semiconductor structure and the process steps can be simplified. With the inclined sidewall of the second part, the present application only forms the insulating layer on the sidewall of the first part to simplify the process steps and reduce the cost.