Stacked Chip Via Insulation for Leakage-Resistant Interconnects
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Solution Overview
Problem
Stacked chip devices face challenges in ensuring reliability due to leakage and transient currents caused by conductor modification and stress accumulation at through-holes, leading to complex manufacturing processes and potential short-circuits.
Innovation Solution
The solution involves a stacked chip device design with non-conductor regions on common electrode patterns facing vias, which reduces via modification and maintains electrical characteristics, and a symmetric structure eliminating the need for direction recognition marks, allowing for undirected use and simplified installation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-holes are formed and filled with conductor to connect conduction patterns vertically, then electrical connection between layers is achieved, but stress accumulation modifies the conductor and causes leakage current or short-circuit
Solution Approach 1:
An insulating layer is introduced as an intermediary between the conductor filling the through-hole and the adjacent conduction patterns. This insulating layer acts as a mediator that prevents direct electrical contact between the conductor and surrounding conductive patterns, thereby eliminating leakage current and transient current while maintaining the vertical electrical connection function of the through-hole
Solution Approach 2:
The insulating layer is formed beforehand to cover the conduction pattern before the through-hole is filled with conductor. This prior cushioning prevents the conductor from directly contacting the conduction pattern, preventing stress-induced modification and electrical breakdown before they can occur
2Adaptability or versatility
If unit devices are arranged horizontally or stacked vertically with directivity, then device functionality is achieved, but direction recognition marks are required complicating manufacturing and mounting
Solution Approach 1:
The patent applies asymmetry by forming insulating layers selectively at specific locations (e.g., only at certain through-holes or only on certain sides of the chip) rather than uniformly throughout. This asymmetric design creates inherent directional characteristics that eliminate the need for direction recognition marks, as the asymmetric insulating structure itself indicates the correct orientation during mounting
Solution Approach 2:
The insulating layer is applied locally at specific positions where needed, such as at particular through-holes or adjacent to specific conduction patterns, rather than uniformly across the entire chip. This local quality approach provides directional indication and prevents leakage current only where required, simplifying the overall manufacturing process
Data Source
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AI summary
The present disclosure relates to a stacked chip device (11) including a first stack unit (B) comprising a plurality of electrode patterns (111, 112) respectively disposed for a unit device region and common electrode patterns (121) formed to be connected to overlap the unit device regions, a second stack unit (A) disposed on a top portion of the first stack unit (B) and comprising a plurality of first conductor patterns (211-216), and a third stack unit (C) disposed on a bottom portion of the first stack unit (B) and comprising a plurality of second conductor patterns (311-316), wherein the first and second conductor patterns (211-216; 311-316) are formed on a plurality of sheets (201-206; 301-306), the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns (211-216; 311-316) are connected vertically through vias (511, 512, 521, 522) formed penetrating through at least some of the sheets.