3D Stacked Semiconductor Package Wiring for Low-Resistance Power Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages with 3D stacked structures face challenges in efficiently connecting and powering multiple semiconductor chips, leading to increased complexity and potential for electrical deterioration due to current resistance and electromigration issues.
Innovation Solution
The semiconductor package design includes a first semiconductor chip with a substrate, lower and upper wiring layers, and through structures that electrically couple these layers, along with external connection terminals, to facilitate power delivery and reduce electrical length, thereby simplifying connections and minimizing IR drop and electromigration deterioration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are stacked in a 3D structure to increase capacity and functionality, then the device can achieve higher integration density, but the electrical connection complexity increases and current resistance problems worsen
Solution Approach 1:
The patent transitions from traditional planar connections to three-dimensional vertical connections through through-substrate vias. Multiple wiring layers (first, second, and third wiring layers) are stacked vertically to establish electrical connections between chips in the Z-direction, enabling higher integration density while managing connection complexity through spatial organization.
Solution Approach 2:
The substrate is divided into multiple functional regions including through-substrate vias, pad regions, and macro cell regions. The wiring structure is segmented into multiple distinct layers with specific functions (power delivery, signal transmission, grounding), allowing independent optimization of each segment to reduce overall system complexity.
2Ease of manufacture
If traditional wiring structures are used in stacked chip packages, then manufacturing processes remain simple, but current resistance and electromigration issues increase
Solution Approach 1:
The patent modifies key electrical parameters by introducing multiple wiring layers with different functions. The first wiring layer is optimized for power delivery with higher current capacity, while the second and third layers handle signals and grounding. This parameter differentiation reduces current density in individual paths, mitigating electromigration and voltage drop issues.
Solution Approach 2:
Through-substrate vias act as intermediary elements that vertically connect the multiple wiring layers and enable electrical coupling between stacked chips. These vias serve as mediators that distribute currents and signals through the substrate thickness, reducing direct horizontal current paths and associated resistance problems.
3Area of moving object
If wiring patterns are densely packed to increase pattern density, then area utilization improves, but electrical deterioration due to IR drop and electromigration worsens
Solution Approach 1:
The patent resolves the density-reliability tradeoff by moving electrical connections from the horizontal plane to the vertical dimension. Through-substrate vias and multiple stacked wiring layers enable three-dimensional current paths, allowing dense horizontal pattern packing while maintaining low resistance through vertical connection pathways that shorten current travel distances.
Solution Approach 2:
Different regions of the substrate are assigned different wiring layer configurations tailored to local requirements. Pad regions utilize through-substrate vias for robust external connections, while macro cell regions employ optimized wiring patterns. This localized optimization allows high pattern density in logic areas while maintaining electrical reliability in connection-critical regions.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip, a second semiconductor chip stacked on the first semiconductor chip, and a plurality of external connection terminals electrically coupled to a lower surface of the first semiconductor chip. The first semiconductor chip includes a substrate including the lower surface and an opposite upper surface, a lower wiring layer in a lower portion of the lower surface including a first plurality of wiring patterns, an upper wiring layer in an upper portion of the upper surface including a second plurality of wiring patterns, a plurality of through structures electrically coupling the lower wiring layer to the upper wiring layer and penetrating the substrate, and a macro cell disposed between the plurality of through structures. At least one of the through structures partially overlaps a wiring pattern of the lower wiring layer in a vertical direction within an overlapping distance from the wiring pattern.