Stacked Semiconductor Chip Interconnect for Void-Resistant Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor packages face challenges in reliability due to issues with internal connection member formation, particularly with the distribution and diffusion of metals like gold, which can lead to voids or cracks, affecting the connectivity and durability of stacked semiconductor chips.
Innovation Solution
The semiconductor package design incorporates a sequential stack of semiconductor chips with internal connection members, where the width of the conductive pads and bumps is strategically sized, and the use of a wetting layer with controlled thickness to ensure proper bonding and minimize the formation of intermetallic compounds that could cause reliability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the conductive pad width is made smaller to reduce package size, then the area occupied by connection structures is reduced, but the reliability of the internal connection member decreases due to increased stress concentration and higher likelihood of voids or cracks
Solution Approach 1:
The patent applies different width dimensions to different components of the internal connection structure. The conductive pad has a first width while the conductive bump has a second width that is greater than the first width. This local variation in dimensions optimizes both space utilization and connection reliability by providing adequate bonding area at the bump interface while keeping the pad footprint compact.
2Strength
If the thickness of the wetting layer is increased to improve bonding, then the strength of the internal connection member increases, but the formation of intermetallic compounds increases which can cause reliability issues
Solution Approach 1:
The patent specifies a controlled thickness range for the wetting layer in the internal connection member. By precisely controlling this parameter within an optimal range, the design achieves sufficient bonding strength while preventing excessive intermetallic compound formation that would compromise connection stability and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability of semiconductor packages by preventing voids and cracks in internal connection members, ensuring stable connectivity between chips and improving the overall durability and performance of the package.
Implementation Method 1
a wetting layer with controlled thickness to ensure proper bonding
Data Source
AI summary
A semiconductor package includes a sequential stack of first and second semiconductor chips, and a first internal connection member that connects the first and second semiconductor chips to each other. The first semiconductor chip includes a first substrate that has a first top surface and a first bottom surface that are opposite to each other, and a first conductive pad on the first top surface. The second semiconductor chip includes a second substrate that has a second top surface and a second bottom surface that are opposite to each other, and a second conductive bump on the second bottom surface. The first internal connection member connects the first conductive pad to the second conductive bump. The first conductive pad has a first width in one direction. The second conductive bump has a second width in the one direction. The first width is smaller than the second width.