Stacked Chip Packaging with Wafer-Level Horizontal Interconnects
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Solution Overview
Problem
Current chip stacking technologies are complex and costly due to the need for vertical connections between stacked chips, which are typically achieved using methods like Through Silicon Via (TSV), Through Glass Via (TGV), or Wire-bond, limiting the efficiency of the packaging process.
Innovation Solution
A chip package and method that involves stacking chip layers with chip connectors having through vias, redistribution layers, and active/passive coupling devices, allowing for horizontal chip stacking without the need for vertical connections, and encapsulating the stack in a molding compound to simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional chip stacking technology using TSV, TGV, or Wire-bond is employed to achieve vertical connections between stacked chips, then reliable electrical connection between layers is improved, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent extracts and eliminates the need for complex vertical connection technologies (TSV, TGV, Wire-bond) by reimagining the chip stacking architecture. Instead of creating vertical pathways through substrates, the invention uses horizontal connections at the wafer level, removing the disturbing complex vertical connection processes from the system while maintaining electrical connectivity through a simpler alternative approach.
Solution Approach 2:
The patent inverts the conventional chip stacking approach by performing connections horizontally at the wafer level before dicing, rather than vertically after individual chip packaging. This inversion of the process sequence and connection orientation simplifies the manufacturing process, allowing multiple chips to be connected simultaneously in a single wafer-level operation rather than requiring complex sequential vertical bonding steps.
2Adaptability or versatility
If Through Silicon Via (TSV) or Through Glass Via (TGV) technologies are used for vertical chip connections, then three-dimensional multi-layer packaging is enabled, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent applies preliminary action by performing all necessary electrical connections between chips while they are still part of the wafer, before the dicing process separates individual chips. This advance connection at the wafer level eliminates the need for costly post-dicing vertical connection processes like TSV or TGV, as all inter-chip routing is completed in advance during the wafer-level packaging operation.
Solution Approach 2:
The patent merges multiple functions into a single wafer-level process: chip interconnection, routing, and packaging are all accomplished simultaneously at the wafer level before dicing. This consolidation of connection and packaging operations eliminates the need for separate, costly vertical via processes, achieving multi-layer packaging capability through integrated horizontal connections rather than sequential vertical stacking operations.
3Productivity
If conventional final assembly stacking is performed with vertical connections, then chip stacking is achieved, but the packaging process becomes complicated and costly
Solution Approach 1:
The patent transitions from vertical three-dimensional stacking to a two-dimensional wafer-level connection approach. By performing all connections horizontally within the wafer plane before dicing, the invention eliminates the need for complex vertical alignment and bonding processes, achieving efficient chip stacking through dimensional transformation of the connection approach from vertical to horizontal.
Data Source
AI summary
A method of forming a package comprises forming a stack of chip layers. Each chip layer has a front side facing away from the carrier substrate. A first chip layer includes a plurality of first chips having first chip contacts on the front side of the first chip layer and chip couplers having through vias. A second chip layer includes a plurality of second chip having second chip contacts on the front side of the second chip layer and coupled to respective ones of at least a first subset of the through vias. The method further comprises forming a redistribution layer on the front side of the first chip layer and dividing the stack of chip layers and the redistribution layer to form a plurality of chip packages. A chip package thus formed include a stack of chips and one or more chip connectors on a singulated redistribution layer.