Stacked Semiconductor Chip Layout for Mismatched Wafer Sizes
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Solution Overview
Problem
In semiconductor devices where two wafers are bonded, mismatches in the sizes of semiconductor elements lead to unnecessary regions, resulting in inefficiencies and waste during the manufacturing process.
Innovation Solution
The semiconductor device design includes a circuit chip and an array chip with the array chip being smaller, where the circuit chip has a metal pad exposed in a second region, allowing for efficient stacking and minimization of unnecessary regions by using a spacer and bonding wire to connect the chips, reducing waste and enabling more chips to be formed on the wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two wafers are bonded with mismatched semiconductor element sizes, then electrical connectivity between chips is achieved, but unnecessary regions increase causing manufacturing inefficiency
Solution Approach 1:
The patent divides the wafer surface into functional regions: a first region for bonding array chips to the circuit wafer and a second region for exposing metal pads. This segmentation allows the circuit wafer to serve dual purposes - providing both bonding surfaces for array chips and exposed pads for wire bonding, thereby eliminating unnecessary regions and improving manufacturing efficiency while maintaining electrical connectivity.
2Productivity
If array chips are made smaller to reduce unnecessary regions, then manufacturing efficiency improves, but chip area for electrical connection decreases
Solution Approach 1:
The patent utilizes the vertical dimension by exposing metal pads on the surface of the circuit wafer in a second region. This allows electrical connections to be established through wire bonding from the top surface, rather than requiring larger chip areas for direct bonding. The metal pads extend beyond the array chip bonding region, enabling compact array chip designs while maintaining adequate connection areas.
Data Source
AI summary
A semiconductor device according to the present embodiment includes a semiconductor chip including a first chip and a second chip. The second chip is joined to the first chip on the first chip such that the second chip is electrically connected to the first chip. The area of the second chip is smaller than the area of the first chip. The second chip is provided in a first region on an upper surface of the first chip and the first chip includes a first pad exposed from the first chip in a second region different from the first region.