Stacked Semiconductor Chip Layout for Wafer Waste Reduction
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Solution Overview
Problem
In semiconductor devices where two wafers are bonded, size mismatches lead to unnecessary regions, resulting in inefficiencies and increased waste during the manufacturing process.
Innovation Solution
The semiconductor device design includes a configuration where the array chip has a smaller lower surface area than the circuit chip, with the barycenter positions of both surfaces offset, and utilizes a spacer to flatten the stepped area, allowing for more efficient stacking and reduced risk of chip tilt during assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two wafers are bonded with mismatched sizes, then bonding is achieved, but unnecessary regions increase causing waste and inefficiency
Solution Approach 1:
The wafer is divided into a first wafer and a second wafer with different sizes, allowing each to be optimized independently. The smaller second wafer can be fully utilized while the larger first wafer provides sufficient bonding area without excessive waste.
Solution Approach 2:
The patent employs asymmetric wafer sizing where the first wafer has a larger area than the second wafer. This asymmetric configuration allows the smaller second wafer to be fully utilized while minimizing the unnecessary region on the larger first wafer, optimizing material usage.
2Loss of substance
If wafer sizes are matched exactly, then waste is minimized, but flexibility in design and assembly is reduced
Solution Approach 1:
The patent deliberately uses asymmetric wafer sizes with the first wafer being larger than the second wafer. This provides design flexibility in terms of chip layout, assembly options, and future modifications while still minimizing waste through optimized area utilization.
Solution Approach 2:
The larger first wafer serves multiple functions: it provides sufficient bonding area for the smaller second wafer, allows for future expansion or modification, and enables different assembly configurations. The extra area becomes a versatile resource rather than waste.
3Ease of operation
If chips are stacked with offset barycenters, then alignment flexibility is improved, but stability during assembly may be compromised
Solution Approach 1:
The patent employs asymmetric positioning where the barycenter of the second wafer is offset from the barycenter of the first wafer in the in-plane direction. This asymmetric offset provides alignment flexibility for different chip configurations while the overall structure maintains stability through careful design of the bonding interfaces.
Data Source
AI summary
A semiconductor device according to the present embodiment includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip has a first upper surface on which a first electrode pad is formed. The second semiconductor chip has a first lower surface on which a second electrode pad directly joined to the first electrode pad is formed and a second upper surface that is opposite the first lower surface and on which a third electrode pad is formed. The area of the first lower surface is smaller than the area of the first upper surface. The barycenter of the first lower surface and the barycenter of the first upper surface are located at different positions in the in-plane direction of the first upper surface.