Stacked Chip Package Wire Layout for Short-Circuit Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in achieving improved electrical reliability and productivity, particularly in the context of miniaturization and standardization, due to the limitations of bonding wire configurations and vertical wire connections.
Innovation Solution
A semiconductor package design featuring a chip stack with offset semiconductor chips connected by bonding wires and vertical wires, where specific portions of these wires have varying widths to optimize electrical connections and reduce the risk of short-circuiting, while maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding wires have uniform width throughout their length, then manufacturing is simpler, but electrical reliability deteriorates due to increased risk of wire sweep and short-circuiting
Solution Approach 1:
The bonding wire is designed with different widths at different locations: a first width at the chip pad contact portion and a second width at the extending portion. This local variation in geometry allows the wire to have optimized properties at each location - wider at the contact point for better electrical connection and narrower at the extending portion to reduce sweep risk and prevent short-circuiting between adjacent wires.
2Reliability
If more wire types (bonding wires and vertical wires) are used for connections, then electrical reliability improves, but manufacturing complexity increases
Solution Approach 1:
The electrical connection system is segmented into two distinct wire types: bonding wires for connecting first chip pads and vertical wires for connecting second chip pads. This segmentation allows each wire type to be optimized for its specific function and connection location, improving overall electrical reliability while enabling specialized manufacturing processes for each wire type.
Solution Approach 2:
Different wire configurations are applied locally based on connection requirements: bonding wires with specific width variations are used for first chip pads, while vertical wires with different width characteristics are used for second chip pads. This localized optimization ensures each connection type achieves its required electrical performance.
3Reliability
If chip pads are arranged in alternating patterns with multiple wire types, then electrical reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The chip pads are segmented into two groups with distinct patterns: first chip pads arranged in a first pattern connected by bonding wires, and second chip pads arranged in a second pattern connected by vertical wires. This segmentation simplifies the manufacturing process by allowing each wire type to follow its own predetermined path to its designated pads, reducing the overall precision requirements compared to a single complex wire routing system.
Data Source
AI summary
Provided is a semiconductor package including a chip stack that includes first and second semiconductor chips stacked in a first direction and offset in a second direction intersecting the first direction, each of the first and second semiconductor chips comprising chip pads in the second direction, a redistribution substrate on the chip stack, first bonding wires connecting the redistribution substrate and the chip pads of the first semiconductor chip, and first vertical wires connecting the redistribution substrate and the chip pads of the second semiconductor chip. Each of the first bonding wires includes a first portion in contact with one of the chip pads of the first semiconductor chip and having a first width, and a second portion extending perpendicularly on the first portion and having a second width, each of the first vertical wires has a third width, and each of the second and third widths is smaller than the first width.