Stacked Pixel and Circuit Chip Wiring for Layout Flexibility
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Solution Overview
Problem
Current semiconductor apparatuses face limitations in performance and quality due to insufficient examination of multi-layer wiring connections between stacked substrates, leading to increased time and cost in the design and manufacturing phases.
Innovation Solution
A semiconductor apparatus is designed with a stack of two chips, where the first chip has a matrix of pixel circuits and the second chip has a matrix of electric circuits, with specific wiring structures and conductive portions to optimize electrical connections, allowing for varied wiring path lengths to enhance layout flexibility and reduce design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-layer wiring is used for connection between substrates, then electrical connections can be established, but design complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional multi-layer wiring structure, utilizing vertical stacking of wiring layers to establish electrical connections between substrates. This dimensional change allows connections without increasing planar footprint, resolving the contradiction between connection reliability and structural complexity.
Solution Approach 2:
The patent implements nested wiring layers where multiple wiring structures are stacked vertically, with each layer containing conductive patterns that connect to corresponding patterns in adjacent layers through via holes. This nesting approach enables complex electrical interconnections while organizing the wiring structure in a compact, manageable manner.
2Adaptability or versatility
If conventional substrate stacking is used, then device integration is achieved, but design and manufacturing time increase
Solution Approach 1:
The patent performs preliminary design of the multi-layer wiring structure and conductor pattern arrangements before substrate fabrication. By pre-planning the three-dimensional wiring architecture and connection points, the design phase is optimized to reduce subsequent manufacturing iterations and accelerate the overall development timeline.
Solution Approach 2:
The patent divides the wiring structure into discrete, modular layers with standardized conductor patterns and connection interfaces. This segmentation allows each layer to be independently designed and manufactured, then stacked and connected, significantly reducing overall design and manufacturing time compared to monolithic structures.
Data Source
AI summary
A semiconductor apparatus includes a stack of a first chip having a plurality of pixel circuits arranged in a matrix form and a second chip having a plurality of electric circuit arranged in a matrix form. A wiring path between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit or a positional relationship between a semiconductor element configuring the pixel circuit and a semiconductor element configuring the electric circuit is differentiated among the electric circuits.