Stacked Semiconductor Chip Redundancy for Yield Improvement
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Solution Overview
Problem
State-of-the-art semiconductor chips with multiple processor cores face challenges in improving yield due to high production costs and area penalties from redundancy repair components, which are less effective for logic blocks and disrupt natural floor planning patterns.
Innovation Solution
A stacked semiconductor chip design where processor cores are distributed among multiple unit chips, with low-yield components logically paired to form functional blocks and high-yield components utilized to their full potential, enhancing overall yield and area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extra processor cores are added to semiconductor chips for redundancy repair, then chip yield is improved, but total chip area increases substantially due to caches and bus interconnect logic circuits
Solution Approach 1:
The invention divides the chip into multiple unit chips, each containing a subset of processor cores. By segmenting the system, redundancy can be implemented at the unit chip level rather than requiring full duplicate cores with all associated caches and interconnect logic on a single chip, thereby reducing the area penalty while maintaining yield improvement benefits
Solution Approach 2:
The invention transitions from a two-dimensional layout on a single chip to a three-dimensional stacked architecture where multiple unit chips are vertically integrated. This dimensional change allows redundancy to be achieved through stacking rather than lateral expansion, significantly reducing the footprint area required for redundant processor cores and their support circuits
2Reliability
If extra processor cores are added for redundancy, then yield is improved, but natural floor planning patterns are disrupted
Solution Approach 1:
By dividing the processor system into multiple unit chips with identical or similar core subsets, the invention maintains consistent floor planning patterns within each unit chip. The segmentation allows each unit to be independently designed and laid out using standard patterns, avoiding the complexity disruption that would result from adding irregular redundant cores to a single chip design
3Speed
If state-of-the-art lithographic dimensions and processing techniques are used to deliver superior performance, then chip performance is improved, but chip yield decreases due to immature technology
Solution Approach 1:
The invention applies different quality levels to different components: unit chips containing processor cores utilize state-of-the-art lithographic dimensions and processing techniques for superior performance, while redundancy repair components and support logic use more mature, higher-yield technologies. This local differentiation allows performance-critical areas to benefit from advanced technology while yield-critical areas rely on stabilized processes
Solution Approach 2:
The invention incorporates redundancy repair components and logic circuits that are designed to compensate for potential failures in advance. By preparing backup mechanisms beforehand using mature technology, the system cushions against yield losses from aggressive scaling, allowing the use of state-of-the-art lithography for performance without suffering the full penalty of immature technology
Data Source
AI summary
A stacked semiconductor chip comprising multiple unit chips contains multiple instances of a first chip component that have a low yield and are distributed among the multiple unit chips. An instance of the first chip component within a first unit chip is logically paired with at least another instance of the first chip component within at least another unit chip so that the combination of the multiple instances of the first chip component across the multiple unit chips constitute a functional block providing the functionality of a fully functional instance of the first chip component. The stacked semiconductor chip may include multiple instances of a second chip component having a high yield and distributed across the multiple unit chips. Multiple low yield components constitute a functional block providing an enhanced overall yield, while high yield components are utilized to their full potential functionality.