Stacked Chiplet Edge Interconnects Without Interposer Packaging
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Solution Overview
Problem
The increasing integration density of semiconductor components poses challenges in connecting integrated circuit dies effectively without relying solely on interposers, which can complicate the packaging process and increase costs.
Innovation Solution
The implementation of edge interconnect features that extend from the circuit region through the seal region into scribe lines, allowing direct connections between neighboring integrated circuit dies without the need for interposers, using hybrid bonding techniques and backside power rails for efficient power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interposers are used to connect integrated circuit dies, then connection between dies is achieved, but packaging complexity and cost increase
Solution Approach 1:
The patent removes the interposer from the packaging structure entirely. Edge interconnect features extend directly from the circuit region through the seal region into scribe lines, enabling neighboring dies to be bonded together without any intermediary substrate. This extraction of the interposer eliminates the associated complexity while maintaining die-to-die connectivity.
Solution Approach 2:
The patent segments the interconnect path into edge interconnect features that extend along the periphery of each die. These edge interconnect features are distributed around the seal region and can be independently formed and configured, allowing flexible routing without requiring a centralized interposer structure.
2Reliability
If interposers are used to connect integrated circuit dies, then connection between dies is achieved, but manufacturing cost increases
Solution Approach 1:
By removing the interposer component entirely, the patent eliminates the need to manufacture, handle, and assemble this additional substrate. The edge interconnect features are formed as part of the standard die fabrication process using existing conductive layers and patterning techniques, thereby reducing manufacturing steps and costs.
Solution Approach 2:
The patent merges the interconnect function with the existing edge structures of the dies. The edge interconnect features utilize the same conductive layers and manufacturing processes already present in the die periphery, combining multiple functions into existing structures rather than adding separate components.
3Productivity
If integration density is increased, then more components are integrated into a given area, but connecting dies through interposers becomes more challenging
Solution Approach 1:
The patent transitions from a centralized vertical connection model through an interposer to a distributed lateral connection model along the die edges. The edge interconnect features extend in the lateral direction along the periphery, utilizing the horizontal dimension more effectively to provide multiple connection points around the seal region, thereby accommodating higher integration density.
Solution Approach 2:
The patent segments the connection interface into multiple distributed edge interconnect features around the periphery of each die. This segmentation provides numerous independent connection points that can be selectively activated, enabling flexible routing and scaling as integration density increases without requiring a proportionally more complex interposer structure.
Data Source
AI summary
Embodiments of the present disclosure provide a stacking edge interconnect chiplet. In one embodiment, a semiconductor device is provided. The semiconductor device includes a first integrated circuit die comprising a first device layer having a first side and a second side opposite the first side, a first interconnect structure disposed on the first side of the first device layer, and a second interconnect structure disposed on the second side of the first device layer. The semiconductor device also includes a power line extending through the first device layer and in contact with the first interconnect structure and the second interconnect structure, and a second integrated circuit die disposed over the first integrated circuit die, the second integrated circuit die comprising a third interconnect structure in contact with the second interconnect structure of the first integrated circuit die.