Stacked Semiconductor Chips Volume Reduction via Adhesive Bonding
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Solution Overview
Problem
The challenge lies in developing semiconductor packages with large capacity and minimized volume, as high integration of semiconductor devices complicates the reduction of design rules, necessitating innovative manufacturing methods to efficiently stack and connect semiconductor chips while maintaining performance and efficiency.
Innovation Solution
A method involving the attachment of semiconductor substrates with adhesive layers, forming cutting grooves to separate chips, and creating molding layers to cover and connect the chips, allowing for the stacking and separation of individual semiconductor packages while minimizing volume and maximizing capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor devices are highly integrated to increase capacity, then the capacity increases, but the design rule reduction becomes difficult and device complexity increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking by vertically arranging multiple semiconductor chips. This dimensional change allows capacity increase without further reducing design rules, as each chip can maintain existing fabrication capabilities while the overall system achieves higher integration through the third dimension.
Solution Approach 2:
The patent divides a single large-scale integrated device into multiple smaller semiconductor chips that are stacked vertically. Each chip can be manufactured using standard design rules, avoiding the need to reduce design rules further, while the segmented structure achieves high capacity through multi-chip integration.
2Quantity of substance
If multiple semiconductor chips are stacked to increase capacity, then the capacity increases, but the package volume may increase
Solution Approach 1:
The patent employs a packaging structure where multiple semiconductor chips are nested vertically within a shared package body. The chips are stacked one on top of another with minimal spacing, and the package encapsulates them efficiently. This nesting approach maximizes capacity within a compact volume by utilizing vertical space rather than expanding horizontally.
3Ease of manufacture
If cutting grooves are formed to separate chips, then chip separation is achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent forms cutting grooves in the substrate before attaching the semiconductor chips. This preliminary action creates predetermined separation paths that simplify subsequent chip extraction and packaging processes. By preparing the substrate structure in advance with grooves already formed, the overall manufacturing complexity is reduced compared to creating separation features after chip attachment.
Data Source
AI summary
A method of forming a semiconductor package having a large capacity and a reduced or minimized volume includes: attaching a semiconductor substrate on a support substrate using an adhesive layer, wherein the semiconductor substrate includes a plurality of first semiconductor chips and a chip cutting region, wherein first and second ones of the plurality of first semiconductor chips are separated each other by the chip cutting region, and the semiconductor substrate includes a first surface on which an active area is formed and a second surface opposite to the first surface; forming a first cutting groove having a first kerf width, between the first and second ones of the plurality of first semiconductor chips, so that the semiconductor substrate is separated into a plurality of first semiconductor chips; attaching a plurality of second semiconductor chips corresponding to the first semiconductor chips, respectively, to the plurality of first semiconductor chips; forming a molding layer so as to fill the first cutting groove; and forming a second cutting groove having a second kerf width that is less than the first kerf width, in the molding layer, so as to separate the molding layer into individual molding layers covering one of the plurality of first semiconductor chips and corresponding one of the plurality of second semiconductor chips.