Stacked Semiconductor Chips With Sidewall Protection for CMP Roll-Off

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Solution Overview

Problem

Current methods for producing semiconductor memory devices face challenges in efficiently stacking chips and forming reliable junctions, leading to issues such as uneven chip thickness and increased risk of roll-off phenomena during chemical mechanical polishing (CMP) processes, which can result in joining failures.

Innovation Solution

The use of a protective film, such as SiO2, SiN, SiC, or BN, is applied to the side faces of the chips and base substrate to prevent excessive polishing during CMP, ensuring even chip thickness and improving the reliability of chip stacking by forming a stacked film structure that alternates between protective films and oxide films, thereby reducing the risk of roll-off and enhancing bonding quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If chips are stacked and subjected to CMP process without protective film, then chip thickness can be reduced and junction electrodes can be formed, but excessive polishing occurs causing uneven chip thickness and roll-off phenomenon leading to joining failures

Engineering Contradiction:
Improvechip thickness uniformityVSAvoidjoining reliability
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A protective film is formed on the side faces of chips before the CMP process to prevent excessive polishing and roll-off phenomenon during the subsequent CMP step, ensuring uniform chip thickness and reliable joining

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protective film acts as an intermediary layer between the polishing pad and the chip side faces, controlling the polishing rate and preventing direct contact that would cause roll-off and uneven thickness

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If protective film is applied to chip side faces, then roll-off phenomenon is suppressed and joining reliability is improved, but device structure becomes more complex

Engineering Contradiction:
Improvejoining reliabilityVSAvoidfilm structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The protective film is applied selectively only to the side faces of the chips where roll-off occurs during CMP, rather than coating the entire chip surface, thus providing protection only where needed and minimizing added complexity

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses the roll-off phenomenon and improves the joining reliability of chip ends, resulting in more stable and efficient semiconductor memory device production by maintaining chip thickness and enhancing bonding quality through the protective film and oxide film stacked structure.

Implementation Method 1

chemical mechanical polishing (CMP) processes

Methodology Applied
Scientific EffectChemical mechanical polishing:

Implementation Method 2

forming a stacked film structure that alternates between protective films and oxide films

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS12199066B2Semiconductor device and method for producing the same
Publication Date: 2025.01.14 KIOXIA CORP
  • US12199066B2 patent drawing
  • US12199066B2 patent drawing
  • US12199066B2 patent drawing

AI summary

A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.