Stacked Identical Chips Latch Chain Addressing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor technology is to efficiently package identically processed chips in a stacked structure while avoiding the need for customization, which increases fabrication costs due to the requirement of unique addresses for each chip.
Innovation Solution
The implementation of a latch chain structure that crosses chip boundaries, allowing for independent addressing of each chip through through-silicon-vias (TSV) and specific patterns of solder bump connections, enabling post-stack address programming and differentiation of chips without shared connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If identical chips are stacked one on top of the other, then fabrication efficiency is improved and mask costs are reduced, but it becomes difficult to distinguish different chips from each other due to the need for unique addresses
Solution Approach 1:
The address space is segmented into two parts: upper address bits are hardwired to specific chips in the stack through dedicated TSV connections, while lower address bits are multiplexed across all chips. This segmentation allows identical chips to be uniquely identified without requiring customization of each chip's logic circuitry.
Solution Approach 2:
A latch chain is introduced as an intermediary component that stores and holds the upper address bits for each chip. The latch chain acts as a mediator between the hardwired address lines and the multiplexed data bus, enabling clear distinction between chips during operation without requiring complex custom logic on each chip.
2Device complexity
If customization is applied to provide unique addresses for each chip, then chip differentiation is achieved, but fabrication costs increase due to different mask sets
Solution Approach 1:
The same standard cell design and identical mask sets are used for all chips in the stack. The universal chip design performs multiple functions: it can be uniquely addressed through the combination of hardwired upper bits and multiplexed lower bits, while maintaining identical fabrication processes across all chips in the stack.
Solution Approach 2:
Instead of changing the structural parameters of each chip through customization, the invention changes the addressing parameters by assigning different combinations of address bits to different chips. The physical chip structure remains identical, but the logical addressing parameters differ, achieving differentiation without customization.
3Quantity of substance
If more components are integrated into a given chip area, then integration density is improved, but design complexities arise including increased interconnections and RC delay
Solution Approach 1:
The invention transitions from a two-dimensional planar interconnection scheme to a three-dimensional stacked architecture. By adding the vertical dimension with TSV connections, the system achieves higher integration density without proportionally increasing lateral interconnection complexity. Addressing is simplified by using the vertical position in the stack as part of the address scheme.
Data Source
AI summary
Methods and structures are provided for packaging identically processed chips in a stacked structure. A latch chain includes a first latch chain, having a single or multiple latches, associated with a first chip. The first latch chain is structured to read data information from the first chip. The latch chain includes a second latch chain, having a single or multiple latches, associated with a second chip. The second latch chain is structured to read data information from the second chip. The first latch chain and the second latch chain are connected to one another such that form a single latch chain that crosses chip boundaries. The first latch chain and the second latch chain are structured to provide identification information for identifying the first chip and the second chip, respectively.