Stacked Electronic Chips With Offset Substrate Connections

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Solution Overview

Problem

Existing electronic devices with stacked chips face challenges due to long electrical connection wires, which lead to electrical losses and sensitivity to electromagnetic effects, particularly when the wires are installed.

Innovation Solution

The electronic device design features a support substrate with first and second electronic chips stacked such that the second chip's rear face extends beyond the periphery of the first chip, allowing for shorter, mechanically resistant electrical connections between the chips and the substrate, with additional connections between the chips to increase link density and reduce wire length.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If chips are offset and connected by electrical connection wires, then electrical links can be established between chips and substrate, but wire length increases causing electrical losses and electromagnetic sensitivity

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidwire length
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent transitions from planar wire-based connections to three-dimensional stacked chip architecture with vertical electrical connection elements. The second chip is positioned above the first chip with its rear face extending beyond the periphery, enabling direct vertical connections to the substrate through the first chip, thereby reducing connection path length and eliminating long wire issues.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces intermediate electrical connection elements (solder balls, pillars, or through-vias) that serve as mediators between chips and substrate. These intermediate elements enable direct electrical contact without long wires, establishing reliable electrical links through vertical pathways rather than lateral wire connections.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If electrical connection wires are used to connect offset chips, then electrical links are established, but mechanical resistance is reduced

Engineering Contradiction:
Improveconnection stabilityVSAvoidmechanical resistance
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent replaces flexible wire-based mechanical connections with rigid electrical connection elements such as solder balls, pillars, or through-vias. These solid structural elements provide both electrical connectivity and enhanced mechanical strength, eliminating the mechanical weakness inherent in wire-based connections.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Reliability

If wire-based connections are used, then electrical links can be established, but the number of electrical links is limited

Engineering Contradiction:
Improveelectrical connection capabilityVSAvoidnumber of electrical links
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stacked chip architecture with the second chip extending beyond the first chip's periphery enables multiple vertical electrical connection pathways. This three-dimensional arrangement allows numerous electrical links to be established simultaneously through the intermediate connection elements, dramatically increasing connection density compared to planar wire-based approaches.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11527511B2Electronic device comprising a support substrate and stacked electronic chips
Publication Date: 2022.12.13 STMICROELECTRONICS PTE LTD
  • US11527511B2 patent drawing
  • US11527511B2 patent drawing
  • US11527511B2 patent drawing

AI summary

An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.