Stacked Multi-Chip Data Processing for Power and Area Limits
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Solution Overview
Problem
Conventional SoC integrated chip architectures face challenges in meeting increasing computing power, power consumption, and storage bandwidth requirements due to limited chip area, and existing stacking solutions fail to optimize power consumption and flexibility for complex application scenarios.
Innovation Solution
A data processing apparatus with stacked chips, including a first chip with a general-purpose processor and dedicated processing units, and a second chip with a dedicated processing unit, connected via inter-chip interconnections, allowing flexible task allocation and computing power enhancement without increasing product volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional SoC integrated chip architecture is used, then chip area is limited, but computing power becomes insufficient
Solution Approach 1:
The patent segments the SoC architecture into multiple independent chips (first chip with general-purpose processor and first dedicated processing unit, second chip with second dedicated processing unit) connected through inter-chip interconnections. This segmentation allows each chip to be optimized for specific functions while collectively providing enhanced computing power that exceeds what a single integrated chip could deliver within limited area constraints.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration approach to a three-dimensional stacked architecture using through-silicon via (TSV) interconnections. By stacking chips vertically and utilizing the third dimension, the system achieves higher computing power density without increasing the horizontal chip area footprint.
2Power
If more components are integrated into SoC, then computing power increases, but power consumption becomes excessively high
Solution Approach 1:
The patent implements local quality by assigning different processing capabilities and power characteristics to different chips. The first chip contains a general-purpose processor and first dedicated processing unit, while the second chip contains a second dedicated processing unit with partially same computing function. This allows tasks to be distributed to appropriate processing units based on their power efficiency characteristics, optimizing overall power consumption while maintaining high computing power.
Solution Approach 2:
The patent enables dynamic task allocation and load balancing between multiple processing units across chips. The system can dynamically adjust which processing unit handles which task based on current power consumption levels, thermal conditions, and computational requirements, thereby maintaining high computing power while optimizing power usage in real-time.
3Quantity of substance
If chip area is limited, then manufacturing costs decrease, but storage bandwidth becomes insufficient
Solution Approach 1:
The patent segments storage and processing functions across multiple chips. The first chip and second chip can each include storage components and processing units, with inter-chip interconnections providing high-bandwidth communication between them. This segmentation allows storage bandwidth to be distributed and scaled without concentrating all storage and processing on a single limited-area chip.
Solution Approach 2:
The patent introduces inter-chip interconnections as intermediaries that provide high-bandwidth data transmission pathways between chips. These inter-chip interfaces act as mediators that enable storage and processing units on different chips to communicate with high bandwidth, effectively extending the storage bandwidth capability beyond what a single chip could provide.
4Adaptability or versatility
If existing stacking technology separates analog and I/O components, then technology independence is achieved, but computing requirements cannot be met
Solution Approach 1:
The patent implements universality by designing the second dedicated processing unit on the second chip to have partially same computing function as the first dedicated processing unit on the first chip. This multi-functionality allows either processing unit to handle various computational tasks, providing task processing flexibility and adaptability while collectively delivering enhanced computing power that exceeds conventional stacking solutions.
Data Source
AI summary
A data processing apparatus includes a first chip and a second chip that are stacked-packaged. The first chip includes a general-purpose processor, a bus, and at least one first dedicated processing unit (DPU). The general-purpose processor and the at least one first dedicated processing unit are connected to the bus. The general-purpose processor is configured to generate a data processing task. The second chip includes a second dedicated processing unit. At least one of one or more units in the at least one first dedicated processing unit and the second dedicated processing unit can process at least a part of the data processing task based on a computing function.