Stacked Semiconductor Chips with Redistribution Layers
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Solution Overview
Problem
The challenge in semiconductor packaging is to minimize package thickness while maintaining functionality and allowing for various connection methods, as existing technologies struggle to efficiently integrate multiple semiconductor chips in a compact form factor.
Innovation Solution
A semiconductor package design that vertically stacks multiple semiconductor chips in a fan-out wafer level package, utilizing a redistribution layer (RDL) and wire bonding to connect the chips, allowing for flexible connection methods and reducing package thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are integrated in a planar configuration, then functionality is improved, but package area increases
Solution Approach 1:
The patent transitions from planar integration to three-dimensional vertical stacking of semiconductor chips. Multiple chips are arranged in layers along the vertical direction, with redistribution layers positioned between chips to enable electrical connections. This dimensional change allows multiple functional chips to be integrated within a compact package footprint, resolving the contradiction between enhanced functionality and increased package area.
2Length of stationary object
If package thickness is reduced for miniaturization, then compactness is improved, but integration of multiple chips becomes difficult
Solution Approach 1:
The patent utilizes vertical stacking to integrate multiple chips within a reduced horizontal footprint. By arranging chips in layers along the vertical axis and using redistribution layers for inter-chip connections, the design achieves compactness while maintaining multi-chip integration capability. The vertical dimension compensates for the reduced thickness, allowing multiple chips to coexist in a compact package.
3Adaptability or versatility
If wire bonding is used to connect chips to redistribution layers, then connection flexibility is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the package into discrete functional segments: semiconductor chips, redistribution layers, and wire bonds. Each component is independently fabricated and then assembled through controlled processes. The wire bonds serve as separate interconnect elements that can be precisely positioned to connect chip pads to redistribution layer contacts, providing connection flexibility while managing manufacturing complexity through modular assembly.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the yield and reduces the thickness of the semiconductor package, enabling efficient integration of multiple chips and improved connectivity, thus addressing the need for compact and functional packaging.
Implementation Method 1
the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds
Data Source
AI summary
A semiconductor package may include a first redistribution layer (RDL); a first semiconductor chip on a top surface of the first RDL, the first semiconductor chip including a first circuit surface and a first bottom surface, the first circuit surface having first I/O pads thereon, the first I/O pads configured to electrically connect the first semiconductor chip to the first RDL via first wire bonds; a second semiconductor chip on the first semiconductor chip, the second semiconductor chip including a second circuit surface and a second bottom surface; and a second RDL on the second semiconductor chip, the second RDL facing both the first circuit surface and the second circuit surface.