Stacked Semiconductor Chips with Insulation Spacer for Compact Packaging
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Solution Overview
Problem
Existing semiconductor devices with multiple stacked chips face challenges in downsizing both vertically and horizontally as the number of chips increases, leading to either increased width or height, which affects packaging efficiency and functionality.
Innovation Solution
A method of fabricating a semiconductor device using four semiconductor chips with specific electrode pad configurations and a spacer placement that allows for electrical connections without shifting, minimizing thickness and area expansion, achieved by securing each chip in a manner that exposes necessary pads for connection while using resin sealing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If many semiconductor chips are stacked shifted from each other stepwise, then the memory capacity is increased, but the width of the package becomes wide
Solution Approach 1:
The patent transitions from horizontal shifting of chips to vertical stacking with insulation spacers, changing the spatial arrangement from 2D lateral displacement to 3D vertical layering. This allows multiple chips to be stacked without increasing package width, as each chip layer is positioned directly above the previous layer with spacer separation.
Solution Approach 2:
Insulation spacers are introduced as intermediary elements between stacked semiconductor chips. These spacers enable vertical stacking while providing electrical isolation and mechanical support, allowing chips to be connected without direct contact and preventing short circuits between adjacent chip layers.
2Quantity of substance
If many semiconductor chips are stacked inserting the insulation spacer between each two semiconductor chips, then the memory capacity is increased, but the height (thickness) of the package becomes high
Solution Approach 1:
Instead of placing insulation spacers between every pair of stacked chips, the patent uses spacers only at specific locations - namely between certain chip layers where electrical isolation is most critical. This partial application of spacers reduces the cumulative height increase while still achieving the necessary electrical isolation for increased memory capacity.
3Ease of operation
If the second and third semiconductor chips are shifted to expose electrode pads, then electrical connections are enabled, but the area of the device increases
Solution Approach 1:
The patent enables electrical pad exposure not through lateral shifting of chips in the horizontal plane, but through vertical positioning differences created by insulation spacers. The spacers lift certain chips vertically, allowing electrode pads to be exposed and accessed from the side without requiring horizontal displacement that would increase device area.
Data Source
AI summary
A method of fabricating a semiconductor device is provided. The semiconductor device has four levels of semiconductor chips stacked on a die pad of a lead frame. Specifically, the first, second, third and fourth semiconductor chips are stacked in turn. The first semiconductor chip shifts from the second semiconductor chip, and the third semiconductor chip shifts from the fourth semiconductor chip. An insulation spacer is placed between the second and third semiconductor chips. The four semiconductor chips are located within the confinement of the die pad. The semiconductor chips, spacer and die pad are sealed in with resin sealing material. Signals are transmitted between the upper semiconductor chip (second semiconductor chip or fourth semiconductor chip) and the lower semiconductor chip (first semiconductor chip or third semiconductor chip) via a plurality of electrode pads connected by wires. Preferably, the first sides, which are the edges of the second and third semiconductor chips, overlap when viewed from the top.