Stacked Semiconductor Chips with TSV Interconnects
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing manufacturing costs while maintaining efficient signal transmission and power distribution, particularly in stacked chip configurations where wiring resistance and manufacturing complexity are concerns.
Innovation Solution
The semiconductor device employs a configuration where first and second chips are stacked with TSVs (through silicon vias) connected to the uppermost wiring layer, allowing for direct connection of power source and ground voltage, and inserting a logic element layer between chip terminals to reduce wiring resistance and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are stacked with conventional wiring connections, then signal transmission and power distribution can be achieved, but wiring resistance increases and manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar wiring connections to three-dimensional vertical connections through TSVs (through-silicon vias). By stacking chips vertically and establishing electrical connections through the thickness dimension of the substrates, the invention reduces wiring resistance and simplifies the interconnect structure compared to traditional lateral wiring approaches.
Solution Approach 2:
The patent implements a nested structure where TSVs are formed within the substrate thickness, with wiring layers nested around them. The first and second wiring layers are positioned at different depths within the substrate, with the second wiring layer nested between the first wiring layer and the TSV bottom, creating a compact three-dimensional interconnect architecture.
2Reliability
If TSVs are connected to the uppermost wiring layer with multiple wiring layers, then power distribution can be achieved, but manufacturing difficulty increases
Solution Approach 1:
The patent performs preliminary actions by forming the TSVs and insulating films before creating the wiring layers. The TSVs are etched and filled with conductive material first, then insulating films are deposited and patterned to define the wiring layer positions. This sequence simplifies subsequent wiring formation and reduces manufacturing complexity.
Solution Approach 2:
The patent applies different structural configurations to different regions of the substrate. The TSV connection structure varies depending on the local wiring layer requirements, with the first wiring layer connected to TSVs at one depth and the second wiring layer connected at another depth, allowing optimized power distribution without uniform complexity throughout the entire structure.
Data Source
AI summary
A semiconductor device includes first and second chips that are stacked such that first surfaces of their element layers face each other. Each chip has a substrate, an element layer on a first surface of the substrate, pads on the element layer, and vias that penetrate through the substrate and the element layer. Each via is exposed from a second surface of the substrate and directly connected to one of the pads. The vias include a first via of the first chip directly connected to a first pad of the first chip and a second via of the second chip directly connected to a second pad of the second chip. The pads further include a third pad of the second chip which is electrically connected to the second pad by a wiring in the element layer of the second chip and to the first pad through a micro-bump.