Stacked Semiconductor Chips Wire-Free Interconnection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor chip stacking technologies face challenges in achieving reliable and compact packaging due to issues with wire bonding, such as wire shorts and reduced package compactness.
Innovation Solution
A stacked structure of semiconductor chips is fabricated with an interconnection member that connects the chips without bonding wires, using a metal layer formed by plating and patterned using laser etching or wet etching, with sidewall-insulating layers and adhesion layers to facilitate efficient electrical connections between chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect semiconductor chips in stacked packages, then electrical connections between chips can be established, but wire shorts and reduced package compactness occur
Solution Approach 1:
The patent extracts and eliminates the wire bonding process from the semiconductor packaging system. Instead of using separate wires to connect chips, the invention integrates the interconnection function directly into the chip structure through conductive patterns formed on the chip surfaces and edges, thereby removing the source of wire shorts and improving package compactness
Solution Approach 2:
The patent merges the electrical interconnection function with the chip structure itself. Conductive patterns are formed that extend from chip bonding pads to the chip edges, allowing direct electrical connection between stacked chips without separate wire bonds. This integration eliminates the harmful effects of wire bonding while maintaining electrical connectivity
2Reliability
If conventional stacking methods are used, then semiconductor chips can be connected, but package compactness and reliability are reduced due to wire bonding requirements
Solution Approach 1:
The patent transitions from planar wire bonding connections to three-dimensional direct connections. Conductive patterns are formed that extend vertically from chip surfaces to edges, enabling direct electrical connection between stacked chips in the vertical dimension. This dimensional change eliminates the need for horizontal wire bonds and improves package compactness
Solution Approach 2:
The patent performs preliminary formation of conductive patterns on chip surfaces and edges before the stacking process. These pre-formed conductive structures are positioned to align with corresponding structures on adjacent chips, enabling direct electrical connection upon stacking without requiring subsequent wire bonding operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and compactness of semiconductor packages by eliminating wire bonding issues, allowing for efficient and cost-effective fabrication of stacked semiconductor devices.
Implementation Method 1
a metal layer formed by plating
Implementation Method 2
patterned using laser etching
Data Source
AI summary
Stacked semiconductor chips include a bonding-wire-free interconnection electrically connecting the semiconductor chips to each. An opening in an adhesion layer between the semiconductor chips may provide a path for the interconnection from a bonding pad on one semiconductor chip, along a sidewall insulation layer of the semiconductor chip, along a sidewall insulation layer of another semiconductor chip to a bonding pad on the other semiconductor chip.