Stacked CIM DRAM Bitcell With BEOL Logic for In-Memory Computing
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently performing computing-in-memory operations, leading to increased data transfer, processing time, power consumption, and chip area requirements, particularly in applications like artificial intelligence and neural networks.
Innovation Solution
A 3D digital CIM DRAM bitcell with stacked substrates and integrated logic circuits performs computing-in-memory operations directly within the memory cell, reducing data transfer and latency by integrating logic circuits with memory cells, allowing concurrent general read/write operations and bit-wise calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred between separate memory and processing units, then data transfer time and power consumption increase, but functional separation allows independent optimization of memory and processing
Solution Approach 1:
The patent combines memory cells and logic circuits into a single integrated structure where memory cells store data and adjacent logic circuits perform computing operations directly on the stored data. This merging eliminates data transfer between separate memory and processing units, reducing both time and power consumption while enabling computing-in-memory operations.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D stacked architecture, placing logic circuits on one substrate and memory cells on another substrate in vertical arrangement. This dimensional change increases integration density and enables direct coupling between memory and logic while maintaining independent optimization capabilities.
2Loss of time
If computing operations are performed outside memory, then data transfer overhead increases, but separate processing units allow more flexible architecture design
Solution Approach 1:
The patent merges memory storage and computing logic into a single bitcell unit, where logic circuits are directly coupled to memory cells. This integration eliminates data transfer overhead between memory and processing units, significantly reducing computing time while the modular bitcell design maintains architectural simplicity.
3Productivity
If more logic circuits are added to perform computing-in-memory, then computing capability improves, but chip area requirements increase
Solution Approach 1:
The patent uses 3D stacked architecture to place logic circuits and memory cells on different substrates in vertical arrangement. This enables high-density integration where multiple logic circuits can be coupled to memory cells without increasing planar chip area, as the expansion occurs in the vertical dimension rather than lateral space.
Solution Approach 2:
The patent implements a nested structure where logic circuits are integrated within the memory bitcell structure itself. The logic circuits are positioned to share space with memory cells through vertical stacking, allowing computing capability to be embedded within the memory architecture without proportional increase in chip area.
4Productivity
If stacked substrate architecture is used, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the integrated circuit into separate substrates: one substrate contains logic circuits while another substrate contains memory cells. This segmentation allows each substrate to be manufactured and optimized independently using appropriate process nodes, then combined through stacking to achieve high integration density without excessive manufacturing complexity.
Data Source
AI summary
A memory includes a logic circuit having a first input, a second input, and an output; and a memory circuit, including: a transistor coupled to the logic circuit, the transistor having a semiconductor layer including a source and a drain; and a storage node having a first connection, a second connection, and a third connection. The source or the drain of the transistor is coupled to the first connection of the storage node, the logic circuit includes one or more transistors in an active region of a substrate, the one or more transistors being front-end of line (FEOL) devices, and the semiconductor layer and the storage node are in back-end of line (BEOL) layers over the substrate.