Stacked Circuit Board Process for Precise Wire Bonding

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Solution Overview

Problem

Conventional circuit board manufacturing processes face challenges in precisely controlling wire-bonding heights to prevent short circuits and increasing package thickness due to uneven pad placement and molding flow interference.

Innovation Solution

A circuit board process involving stacked substrates with metal layers and conductive structures, where the first and third pads are not on the same plane, allowing for precise wire bonding and reducing interference, and a metal layer covers the cavity to prevent contamination and simplify manufacturing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If pads are disposed on the same surface of the substrate, then the wire-bonding process becomes complex and requires precise height control, but this leads to short circuit risks and increased package thickness

Engineering Contradiction:
Improvewire-bonding process complexityVSAvoidshort circuit prevention
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies dimensionality change by moving pads from a two-dimensional same-surface arrangement to a three-dimensional distributed arrangement across multiple surfaces and layers. Specifically, pads are disposed on different surfaces (upper surface 113 and bottom surface 114) and different layers (substrate 111 and heat dissipating plate 112) of the carrier, transforming the pad layout from planar to spatial distribution. This resolves the wire-bonding complexity and short circuit risks by naturally separating bonding heights through vertical layering rather than relying on precise height control in a single plane.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of operation

If pads are disposed on the same surface of the substrate, then all pads can be accessed from one side, but this causes wire-bonding height exaggeration and increased package thickness

Engineering Contradiction:
Improvepad accessibilityVSAvoidpackage thickness
Core Design Contradiction:
Ease of operationVSLength of stationary object

Solution Approach 1:

The patent utilizes the vertical dimension by distributing pads across multiple layers and surfaces. Pads are located on the upper surface 113 of the substrate 111, bottom surface 114 of the substrate, and upper surface 118 of the heat dissipating plate 112. This three-dimensional pad distribution allows wire bonding to occur at different vertical levels, eliminating the need for exaggerated wire-bonding heights and reducing overall package thickness while maintaining pad accessibility through multiple access paths.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If a conventional cavity structure is used without additional masks, then manufacturing is simpler, but contamination from impurities and electroplating solutions cannot be prevented

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidcontamination prevention
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

The patent applies multi-functionality by making the cavity structure itself serve multiple purposes: it provides the intended cavity function while simultaneously acting as a protective mask during electroplating and manufacturing processes. The cavity structure 115, formed by the substrate opening and heat dissipating plate, prevents contamination from impurities, pollutants, electroplating solutions, and solvents without requiring additional separate mask components, thus achieving both manufacturing simplicity and contamination prevention through a single integrated structure.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8132320B2Circuit board process
Publication Date: 2012.03.13 ADVANCED SEMICON ENG INC
  • US8132320B2 patent drawing
  • US8132320B2 patent drawing
  • US8132320B2 patent drawing

AI summary

A circuit board process is provided. In the circuit board process, a first substrate and a second substrate are stacked to form a cavity for accommodating chips. The top of the cavity is covered by a third metal layer that serves as a mask. The first substrate has a base, a first metal layer, a second metal layer, and at least a first conductive structure, and the first metal layer is patterned to form a first circuit layer having a number of first pads. The second substrate, at least an insulation layer and a third metal layer are laminated to the first substrate with a common opening in-between, and the third metal layer covers the common opening. A third circuit layer having a number of third pads is formed on the second substrate. The first pads and the third pads are not on a same plane for wire bonding.