Stacked Integrated Circuit Interconnects via Trench Isolation
Solution Overview
Problem
Current methods for stacking and interconnecting integrated circuits are complex and impractical, particularly due to the challenges of aligning and connecting large wafers, as well as the inflexibility and high cost of conventional interconnect materials, which hinder the efficient production of three-dimensional integrated circuits.
Innovation Solution
A method involving the formation of trenches in wafers, filling them with insulating material, thinning to create isolated regions, and then assembling wafers to form a stack where collective holes are made to introduce conductive material for lateral electrical connections, allowing for flexible and efficient interconnection without the need for selective oxides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional interconnect materials and methods are used for wafer stacking, then electrical interconnection is achieved, but the process becomes complex and costly due to multiple steps for through-via formation and alignment challenges
Solution Approach 1:
The invention segments the interconnection process into two distinct phases: (1) forming isolated regions with insulating material during wafer fabrication to electrically isolate conductive zones, and (2) creating through-vias after wafer stacking to establish electrical connections. This segmentation allows each phase to be optimized independently, reducing overall process complexity while maintaining reliable interconnection.
Solution Approach 2:
The invention performs preliminary action by creating isolated regions filled with insulating material during the wafer fabrication stage, before the wafers are stacked. This preliminary isolation of conductive zones simplifies subsequent alignment and connection operations during stacking, as the conductive areas are already defined and protected from unintended electrical contact.
2Reliability
If through-vias are formed in each wafer before assembly, then electrical interconnection is possible, but the manufacturing process becomes expensive and complex requiring multiple steps
Solution Approach 1:
The invention inverts the conventional sequence by not forming through-vias in each wafer before assembly. Instead, it creates isolated regions during fabrication, stacks the wafers with their conductive zones aligned, and then forms through-vias collectively after stacking. This inversion eliminates the need for complex pre-assembly via formation in each wafer, significantly reducing manufacturing steps and costs.
Solution Approach 2:
The invention merges the through-via formation step to be performed collectively on the stacked wafer assembly rather than individually on each wafer. This combining of operations reduces the total number of manufacturing steps, lowers costs, and simplifies the overall process while maintaining reliable electrical interconnection between stacked wafers.
3Productivity
If large wafers are aligned and assembled, then three-dimensional integration is achieved, but the operation becomes delicate and difficult due to size and lack of flexibility
Solution Approach 1:
The invention applies local quality by creating isolated regions with insulating material at specific locations where conductive zones exist on each wafer. This localized isolation ensures that only the intended conductive areas are electrically connected during stacking, while other regions remain isolated. This approach simplifies alignment requirements and makes the assembly operation more robust despite the large wafer size.
4Reliability
If interconnect material such as solder is used, then electrical connection is achieved, but flexibility and ductility are insufficient for assembling large wafers
Solution Approach 1:
The invention introduces an intermediary approach by using isolated regions filled with insulating material as a mediator between conductive zones on stacked wafers. This intermediary structure provides mechanical support and defined alignment references, enabling flexible assembly of large wafers while ensuring reliable electrical connection through the subsequently formed through-vias. The insulating material acts as a buffer that accommodates assembly variations.
Data Source
Figure 1A~1D
Figure 1E~1F
Figure 1G~1H
AI summary
Embodiments of the invention relate to a method for stacking and interconnecting integrated circuits, comprising steps of providing at least two substrates (10-10"), forming a trench (70-70") in each substrate, filling each trench with an insulating material, forming on each substrate at least one conductive area (50-51", 50a-51b"), thinning each substrate until reaching at least the bottom of the trench, to obtain in each substrate an electrically isolated region delimited by the trench, assembling the substrates, making at least one hole (71) through the assembled substrates such that the hole passes at least partially through the conductive areas and through the isolated region of each substrate, and filling the hole with an electrically conductive material to obtain a conductive column (81-81b) which passes through the isolated region of each substrate and is in lateral electrical contact with the conductive areas.