Stacked High-Voltage Clamp for ESD Protection With Low Leakage
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Solution Overview
Problem
Integrated circuits are vulnerable to damage from electrostatic discharge (ESD) and high voltage spikes, which existing high voltage clamps may not adequately protect, especially as semiconductor processes scale down and drain-to-source voltage limits of transistors decrease.
Innovation Solution
A high voltage clamp design using stacked transistors with resistive and capacitive voltage dividers to bias and trigger the transistors, providing a low-impedance path to ground during voltage transients, and allowing the use of transistors with lower drain-to-source voltage limits, while also enabling operation in both active and non-active modes to conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage clamp is used to protect integrated circuits from ESD and voltage spikes, then protection reliability is improved, but power loss increases due to leakage current during normal operation
Solution Approach 1:
The clamp circuit dynamically switches between high-impedance state during normal operation and low-impedance state during ESD events. The biasing circuit adjusts transistor gate voltages based on operating conditions, making the protection mechanism adaptive rather than static, thereby reducing unnecessary power consumption while maintaining protection capability.
Solution Approach 2:
The invention changes the impedance parameter of the clamp circuit based on operating conditions. During normal operation, the clamp maintains high impedance to minimize leakage current. During ESD events, the impedance switches to low impedance to provide effective protection. This parameter change is controlled by detecting voltage conditions and adjusting transistor biasing accordingly.
2Reliability
If transistor voltage limits are increased to handle higher ESD events, then protection capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The protection function is segmented into multiple transistors with different voltage ratings rather than using a single high-voltage transistor. Each transistor handles a portion of the voltage stress, allowing the use of standard-voltage transistors to achieve overall high-voltage protection capability. This segmentation reduces manufacturing complexity while maintaining protection effectiveness.
Solution Approach 2:
The biasing circuit acts as an intermediary that distributes voltage stress across multiple transistors. By carefully controlling gate voltages, the biasing circuit ensures that no single transistor exceeds its voltage rating while collectively providing protection against high-voltage ESD events. This mediator approach simplifies device selection and manufacturing.
3Reliability
If the clamp remains active continuously to provide protection, then protection reliability is improved, but power consumption increases
Solution Approach 1:
The clamp circuit operates periodically rather than continuously, activating only when ESD events are detected. The biasing circuit monitors voltage conditions and enables protection only when needed, creating a periodic on-off operation pattern. This reduces average power consumption while maintaining protection reliability through timely activation.
Solution Approach 2:
The clamp circuit is self-regulating through its biasing design. The same circuitry that provides protection also detects when protection is needed and controls its own activation state. The biasing automatically adjusts transistor states based on voltage conditions, eliminating the need for external control signals and enabling autonomous power management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively suppresses high voltage transients and ESD events by providing a low-impedance path to ground, reducing voltage stress on transistors and conserving power by disabling the leakage current when not needed.
Implementation Method 1
a resistive voltage divider configured to bias a gate of the first transistor and a gate of the second transistor based on a supply voltage on the power bus
Implementation Method 2
a capacitive voltage divider configured to turn on the first and second transistors in response to a voltage transient on the power bus exceeding a trigger threshold voltage
Implementation Method 3
An ESD event may occur due to transfer of charge from an object or a person to the integrated circuit
Data Source
AI summary
In certain aspects, a clamp includes first and second transistors coupled in series between a power bus and a ground. The clamp also includes a resistive voltage divider configured to bias a gate of the first transistor and a gate of the second transistor based on a supply voltage on the power bus. The clamp further includes a capacitive voltage divider configured to turn on the first and second transistors in response to a voltage transient on the power bus exceeding a trigger threshold voltage.