Stacked Class-D Oscillators for Low-Parasitic Galvanic Isolation
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Solution Overview
Problem
Traditional galvanic isolation techniques in semiconductor packages face limitations in maximum surge isolation voltage and common-mode transient immunity due to capacitive parasitics, which are insufficient for emerging applications requiring higher isolation ratings and data rates.
Innovation Solution
The implementation of package-scale galvanic isolation using RF coupling between side-by-side co-packaged semiconductor chips, where micro-antennas exploit near-field electromagnetic coupling with a molding compound as the isolation barrier, allowing for increased isolation ratings and reduced capacitive parasitics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chip-scale isolators use thick dielectric layers (silicon dioxide or polyimide) as isolation barrier, then galvanic isolation is achieved, but the maximum manufacturable dielectric thickness limits the isolation rating and parasitic capacitance degrades CMTI performance
Solution Approach 1:
The patent divides the isolation barrier into multiple thin dielectric layers (first dielectric layer and second dielectric layer) stacked between the primary and secondary circuits. This segmentation allows achieving high isolation rating (e.g., 10 kV or 20 kV) without relying on a single thick dielectric layer, thereby reducing parasitic capacitance and improving CMTI performance while maintaining manufacturability.
2Productivity
If higher switching frequencies are used with wideband power devices (GaN HEMT and SiC MOSFETs), then data rate is improved, but CMTI requirement increases beyond 200 kV/μs which traditional isolators cannot meet
Solution Approach 1:
The patent changes the structural parameters of the isolation barrier by using multiple thin dielectric layers with optimized thicknesses and materials. This parameter optimization reduces parasitic capacitance to levels that enable CMTI performance beyond 200 kV/μs, supporting higher switching frequencies and data rates required by wideband power devices.
3Ease of manufacture
If a single thick dielectric layer is used for galvanic isolation, then manufacturing is simplified, but the maximum manufacturable thickness limits the surge isolation voltage capability
Solution Approach 1:
The patent segments the isolation barrier into multiple thin dielectric layers that can be manufactured using standard semiconductor fabrication processes. Each thin layer is within the manufacturable thickness range, yet their series combination achieves high surge isolation voltage ratings (10 kV or 20 kV) without compromising ease of manufacture.
4Reliability
If thick dielectric layers are used to achieve high isolation rating, then surge withstanding capability is improved, but capacitive parasitics increase and degrade CMTI performance
Solution Approach 1:
The patent divides the total dielectric thickness into multiple thin layers, maintaining the same total thickness for surge withstanding capability while reducing parasitic capacitance. The series connection of multiple thin dielectric layers provides equivalent or superior breakdown voltage resistance compared to a single thick layer, but with lower parasitic capacitance due to reduced interface effects and optimized material properties.
Solution Approach 2:
The patent uses composite dielectric structures with different material properties in each layer. By selecting materials with appropriate breakdown strengths and low loss tangents for each layer, the composite structure achieves high surge withstanding capability while minimizing overall parasitic capacitance, thereby improving CMTI performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the isolation rating and common-mode transient immunity performance while maintaining competitive data rates, achieving reinforced isolation and higher power consumption efficiency compared to traditional chip-scale insulation schemes.
Implementation Method 1
RF coupling between side-by-side co-packaged semiconductor chips, where micro-antennas exploit near-field electromagnetic coupling with a molding compound as the isolation barrier
Implementation Method 2
a first capacitor coupled in parallel with the first coil; and a second capacitor coupled in parallel with the second coil
Data Source
AI summary
An oscillator circuit includes a total of N (N≥2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.