Stacked Class-D Oscillators for High-Isolation Capacitive Coupling
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Solution Overview
Problem
Traditional galvanic isolation techniques in semiconductor packages face limitations in maximum surge isolation voltage and common-mode transient immunity due to inherent parasitic effects, which are insufficient for emerging applications requiring higher isolation ratings and data rates.
Innovation Solution
The implementation of capacitively-coupled stacked Class-D oscillators with capacitive synchronization between multiple oscillator circuits, utilizing standard CMOS transistors and capacitors to reduce oscillation amplitude and current consumption, while achieving enhanced isolation and data transmission capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional galvanic isolation techniques use thick dielectric layers (silicon dioxide or polyimide) as isolation barrier, then isolation rating is improved, but parasitic capacitive effects increase which degrades common-mode transient immunity
Solution Approach 1:
The patent divides the galvanic isolation barrier into multiple discrete capacitor stages (first capacitor, second capacitor, third capacitor) arranged in series. Each capacitor provides a portion of the total isolation voltage rating, allowing the system to achieve high isolation ratings (e.g., 10 kV or 20 kV) while keeping individual capacitor parasitics low. This segmentation enables the total isolation capability to be distributed across multiple low-parasitic components rather than relying on a single thick dielectric layer.
Solution Approach 2:
The patent changes the fundamental parameter of the isolation barrier from a continuous thick dielectric layer to a discrete multi-stage capacitive structure. By transitioning from a single thick capacitor to multiple thinner capacitors in series, the system maintains or improves isolation rating while reducing total parasitic capacitance. The series configuration allows the voltage stress to be distributed across multiple smaller capacitance values, achieving both high voltage withstand capability and low parasitic effects.
2Reliability
If capacitor-based galvanic isolation is used, then isolation barrier is achieved, but data rate and common-mode transient immunity are limited due to capacitive parasitics
Solution Approach 1:
The patent segments the isolation barrier into multiple capacitive stages that can be optimized for different frequency ranges. Each capacitor stage contributes to the overall isolation while presenting a smaller individual capacitive load to the signal path. This segmentation reduces the total effective parasitic capacitance seen by high-speed signals, enabling higher data rates to be achieved through the isolated barrier compared to traditional single-stage capacitor approaches.
3Reliability
If chip-scale isolators with thick dielectric layers are used, then galvanic isolation is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs standard CMOS transistors and capacitors that serve dual functions: they constitute the oscillator circuits for signal generation and simultaneously form the galvanic isolation barrier through their capacitive coupling. The same standard CMOS components used for normal circuit functionality are leveraged to provide the isolation capability, eliminating the need for separate specialized isolation structures or thick dielectric layers that would increase manufacturing complexity.
Solution Approach 2:
The patent uses standard CMOS capacitor structures that are already well-established in conventional semiconductor manufacturing processes. By copying and utilizing existing standard cell library components (transistors and capacitors) for both signal processing and isolation functions, the design avoids introducing new manufacturing complexities or requiring specialized process steps for creating thick dielectric isolation barriers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the isolation rating and common-mode transient immunity beyond traditional methods, enabling higher data rates and multi-channel capabilities with reduced manufacturing costs and time, using standard CMOS technology.
Implementation Method 1
capacitively-coupled stacked class-D oscillators for galvanic isolation
Implementation Method 2
a first coil coupled between a second load path terminal of the first transistor and a second load path terminal of the second transistor; and a first capacitor coupled in parallel with the first coil
Data Source
AI summary
An oscillator circuit includes a total of N (N≥2) class-D oscillator circuits stacked together between a supply voltage node and a reference voltage node. The output ports of adjacent class-D oscillator circuits in the disclosed oscillator circuit are coupled together by capacitors to ensure frequency and phase synchronization for the frequency signals generated by the class-D oscillator circuits. Compared with a reference oscillator circuit formed of a single class-D oscillator circuit, the oscillation amplitude of each of the class-D oscillator circuits in the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit, and the current consumption of the disclosed oscillator circuit is 1/N of that of the reference oscillator circuit.