Stacked Clock Driver Charge Recycling for Low-Power Distribution
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Solution Overview
Problem
Clock distribution networks in electronic circuits, such as microcontrollers and smart cards, consume a significant portion of power due to high switching activity and large switching capacitance, leading to substantial dynamic power consumption and leakage currents, which is undesirable for low-power devices.
Innovation Solution
A stacked clock driver circuit that performs clock signal charge recycling by generating output clock signals that swing between different voltage ranges, driving load networks of different semiconductor types, thereby reducing power consumption through energy recycling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock distribution networks are used with full-swing clock signals, then reliable clock signal distribution is achieved, but power consumption increases significantly due to high switching activity and large switching capacitance
Solution Approach 1:
The clock distribution network is segmented into multiple voltage domains (first voltage range and second voltage range). The stacked clock driver circuit divides the full-swing clock signal distribution into half-swing segments, where each segment operates in a different voltage range. This segmentation reduces the switching capacitance in each domain while maintaining reliable clock signal distribution across the entire system.
Solution Approach 2:
The patent changes the voltage parameter of clock signals by generating output clock signals that swing between different voltage ranges (e.g., first output clock signal swings between VDD/2 and VDD, second output clock signal swings between 0 and VDD/2). This parameter change reduces the dynamic power consumption while maintaining signal integrity through the stacked driver architecture.
2Reliability
If full-swing clock signals are distributed across the circuit, then all load networks can be reliably driven, but dynamic power consumption increases due to large switching capacitance
Solution Approach 1:
Load networks are segmented into two groups: those driven by clock signals in the first voltage range and those driven by clock signals in the second voltage range. The stacked clock driver circuit independently drives each group with appropriately scaled voltage swings, reducing the overall switching capacitance while ensuring all load networks receive reliable clock signals for proper operation.
3Reliability
If high voltage swing clock signals are used, then signal integrity is maintained, but short-circuit power consumption increases due to frequent switching
Solution Approach 1:
The patent changes the voltage swing parameter of clock signals from full-swing (0 to VDD) to half-swing in stacked configuration. The first output clock signal swings between VDD/2 and VDD, while the second output clock signal swings between 0 and VDD/2. This parameter change reduces the voltage differential that buffers must switch, thereby reducing short-circuit current while maintaining signal integrity through proper voltage domain isolation.
Data Source
AI summary
Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described.