Stacked Clock Doubler Circuit for 50% Duty Cycle Stability
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Solution Overview
Problem
Conventional frequency doubler circuits in radiation-rich environments face challenges in maintaining a 50% duty cycle for clock signals, leading to suboptimal duty cycle correction and increased phase noise, which affects the performance of high-speed ADC applications.
Innovation Solution
A clock doubler circuit is designed with multiple stages of duty cycle correction using digital quadrature generator circuits, frequency doubler circuits, and stacked duty cycle correction circuits, employing PMOS and NMOS transistors to generate a 50% duty cycle clock signal without phase-locked loops (PLLs) or operational amplifiers, thereby reducing noise and improving phase performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional frequency doubler circuits are used in radiation-rich environments, then the circuit can operate, but the duty cycle cannot be maintained at 50%, leading to increased phase noise
Solution Approach 1:
The frequency doubler circuit is divided into multiple independent stages: a first frequency doubler stage and a second frequency doubler stage, where each stage performs partial frequency multiplication. This segmentation allows better control of duty cycle at each stage, preventing the accumulation of phase noise that occurs in single-stage conventional designs.
Solution Approach 2:
The circuit employs periodic switching of PMOS and NMOS transistor pairs in a complementary manner, where transistors are turned on and off in alternating cycles. This periodic action ensures that each transistor conducts for exactly half the cycle, maintaining 50% duty cycle and eliminating the phase noise generated by duty cycle distortion in conventional continuous operation circuits.
2Object-generated harmful factors
If duty cycle correction circuits are added to maintain 50% duty cycle, then phase noise is reduced, but device complexity increases
Solution Approach 1:
The frequency doubling function and duty cycle correction function are merged into a single integrated circuit structure. The same PMOS and NMOS transistor pairs that perform frequency multiplication also inherently correct the duty cycle, eliminating the need for separate duty cycle correction circuits and reducing overall device complexity.
Solution Approach 2:
The PMOS and NMOS transistor pairs serve multiple functions simultaneously: they act as frequency multipliers, duty cycle correctors, and phase aligners. This multi-functionality reduces the total component count and circuit complexity compared to conventional designs that require separate circuits for each function.
3Measurement precision
If multiple stages of frequency doubling are used, then frequency multiplication accuracy is improved, but device complexity increases
Solution Approach 1:
The second frequency doubler stage is nested within the output of the first stage, where the first stage generates an intermediate frequency signal that is then processed by the second stage. This nested arrangement allows systematic frequency multiplication (e.g., 2x then 2x again for 4x total) with better accuracy control at each nesting level, while sharing common circuit resources to limit complexity growth.
Data Source
AI summary
A system for correcting a duty cycle comprises a digital quadrature generator circuit, a frequency doubler circuit, a first duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit, and a second duty cycle correction circuit coupled between the digital quadrature generator circuit and the frequency doubler circuit. The first duty cycle correction circuit comprises a first stacked duty cycle correction circuit and the second duty cycle correction circuit comprises a second stacked duty cycle correction circuit.