Stacked CMOS Image Sensor Layout for Centered Arrays
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Solution Overview
Problem
Conventional CMOS image sensors have a layout that prioritizes keeping similar components together, leading to a non-centered sensor array and a larger footprint, which is problematic for edge mount sensors like imaging barcode scanners, limiting their integration into thinner mobile devices.
Innovation Solution
A CMOS image sensor design with a centered sensor array and split Analog-to-Digital (ADC) modules positioned on either side of the sensor array, along with a video sequence converter to accommodate column-by-column digital output for traditional row-by-row display devices, achieving a minimum height and versatile integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If similar components are kept together in the layout, then manufacturing and signal routing are simplified, but the sensor array cannot be centered on the die and the footprint increases
Solution Approach 1:
The patent transitions from a conventional planar layout to a three-dimensional stacked architecture. The sensor array is positioned on a first substrate while ADC modules and digital logic are placed on a second substrate stacked above it. This vertical dimensionality change allows the sensor array to be centered on the first substrate without requiring peripheral placement of ADC modules, thereby reducing the horizontal footprint while maintaining manufacturing simplicity through standardized stacking processes.
Solution Approach 2:
The patent divides the sensor system into separate functional modules on different substrates: the sensor array on the first substrate and the ADC/digital logic modules on the second substrate. This segmentation allows independent optimization of each module's position and size, enabling the sensor array to be centered while ADC modules are positioned separately on the stacked substrate, thus reducing overall footprint without compromising manufacturing ease.
2Manufacturing precision
If the sensor array is centered on the die, then mechanical alignment and optical performance are improved, but keeping similar components together becomes difficult and footprint increases
Solution Approach 1:
By moving ADC modules and digital logic to a second substrate stacked above the first substrate, the patent enables the sensor array to be perfectly centered on the first substrate without requiring peripheral component placement. The vertical stacking eliminates the horizontal space requirements that would otherwise be needed to accommodate similar components near the centered array, thus reducing footprint while maintaining precise centering.
Solution Approach 2:
The patent introduces a second substrate as an intermediary layer that hosts the ADC modules and digital logic circuits. This intermediary substrate acts as a mediator that separates the sensor array from its processing components, allowing the array to be centered on the first substrate while the processing components are positioned on the second substrate, thereby achieving both centering precision and compact footprint.
3Adaptability or versatility
If ADC modules are positioned away from the sensor array center, then layout flexibility is improved, but the sensor height and integration complexity increase for thin device integration
Solution Approach 1:
The patent positions ADC modules and digital logic on a second substrate stacked vertically above the first substrate containing the sensor array. This vertical arrangement in the third dimension provides layout flexibility for component placement while minimizing the horizontal footprint and reducing overall sensor height compared to lateral arrangements, enabling integration into thin mobile devices.
Solution Approach 2:
The patent implements a nested substrate structure where the second substrate containing ADC modules is stacked and aligned above the first substrate containing the sensor array. This nesting arrangement allows compact integration of multiple functional layers in a vertical configuration, reducing the overall sensor height while maintaining layout flexibility for component positioning.
Data Source
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AI summary
A stacked die CMOS image sensor comprises a sensor die having a sensor array and opposing faces, a sensor die upper face and a sensor die lower face; a memory die, the memory die having a first opposing face that is adjacent to the sensor die lower face, wherein the memory die is electrically connected to the sensor die through silicon vias; a processing die that is electrically connected to the memory die through silicon vias, wherein the processing die comprises a central processing unit (CPU) that is configured to output digital image data and perform control functions; and a video sequence converter that is electrically connected to the output of the sensor die, wherein the video sequence converter is configured to convert digital image data in a column-by-column image format to digital image data in a row-by-row image format.