Stacked CMOS Contact Metals for Lower Source-Drain Resistance
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Solution Overview
Problem
Existing CMOS devices face challenges in minimizing resistance at the metal-semiconductor interface, particularly in complementary metal-oxide-semiconductor (CMOS) devices, where different metals are required for N-type and P-type source/drain regions to optimize performance, but current solutions either compromise one type or lead to increased resistance due to doping limitations and integration issues with germanium.
Innovation Solution
The use of a first metal layer interfacing with N-type source/drain regions and a second metal layer interfacing with P-type source/drain regions, with the second metal layer being deposited over the first metal layer, to minimize resistance while optimizing both conductivity types, using metals like titanium, nickel, cobalt, molybdenum, or tungsten for each type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single metal is used for both N-type and P-type source/drain regions, then the manufacturing process is simplified, but the resistance at the metal-semiconductor interface increases for one of the conductivity types
Solution Approach 1:
The contact structure is segmented into multiple metal layers with different materials optimized for different conductivity types. The first metal layer (e.g., tungsten) provides good contact with P-type regions, while the second metal layer (e.g., titanium, nickel, cobalt, or molybdenum) provides good contact with N-type regions. This segmentation allows each metal to be independently optimized for its intended interface, resolving the contradiction between manufacturing simplicity and interface resistance.
Solution Approach 2:
The contact structure uses a composite material approach by stacking different metal layers together. This composite structure combines the advantages of different metals: tungsten provides low resistance and good P-type interface, while transition metals like titanium, nickel, cobalt, or molybdenum provide low resistance and good N-type interface. The composite contact structure achieves low resistance for both conductivity types simultaneously.
2Reliability
If different metals are used for N-type and P-type source/drain regions, then the resistance at the metal-semiconductor interface is minimized for both conductivity types, but the device complexity increases
Solution Approach 1:
The first metal layer (e.g., tungsten) serves a dual function: it provides the primary contact interface for P-type source/drain regions and serves as an underlying layer for the second metal layer that contacts N-type regions. This multi-functionality reduces the need for completely separate contact structures for different conductivity types, thereby reducing overall device complexity while maintaining low resistance interfaces.
Solution Approach 2:
Instead of using different metals in the same lateral plane, the solution moves to a vertical dimension by stacking metal layers. The first metal layer contacts P-type regions directly, while the second metal layer is deposited over the first metal to contact N-type regions. This vertical stacking approach simplifies the manufacturing process compared to lateral differentiation, as it uses sequential deposition steps that can be applied uniformly across the device.
3Reliability
If the doping level of source/drain regions is increased to reduce resistance, then the resistance decreases, but dopant clusters form and diffusion into the channel increases off-state current
Solution Approach 1:
The patent introduces metal layers as intermediary materials between the external contact and the semiconductor source/drain regions. These metal layers (particularly the second metal layer with transition metals like titanium, nickel, cobalt, or molybdenum) serve as mediator materials that provide low-resistance interfaces without requiring extreme doping levels. This intermediary approach allows resistance reduction while avoiding the harmful effects of high doping such as cluster formation and channel diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced resistance in both N-type and P-type source/drain regions, enhancing drive current and efficiency by individually optimizing the metal-semiconductor interfaces, thereby improving the overall performance of CMOS devices.
Implementation Method 1
The interface between metal and semiconductor is a key source of undesired resistance through a transistor. Selecting the proper metal materials to decrease the resistance is not without issue.
Data Source
AI summary
Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of forming CMOS devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first metal over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, a second metal over the second source region and the second drain region, and the first metal over the second metal.