Stacked Nanostructure CMOS Contacts for Flexible Signal Routing

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Solution Overview

Problem

Existing complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) face limitations in signal routing flexibility due to restricted interconnection options, particularly at advanced technology nodes where geometric size is decreased, necessitating improved methods for semiconductor device fabrication.

Innovation Solution

The introduction of a novel semiconductor device structure with both frontside and backside source/drain contacts, allowing for flexible signal routing by connecting source/drain features on both the frontside and backside of the device, enhancing interconnection options.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional frontside-only source/drain contacts are used, then device structure is simple, but signal routing flexibility is limited

Engineering Contradiction:
Improvesignal routing flexibilityVSAvoiddevice structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extends the interconnection architecture from a single-plane (frontside-only) configuration to a multi-plane configuration by adding backside source/drain contacts. This dimensional expansion allows signals to be routed through multiple planes (frontside and backside), fundamentally increasing routing flexibility without proportionally increasing device complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the source/drain contact structure into separate frontside and backside components. By segmenting the contact architecture into distinct frontside contacts and backside contacts, the system enables independent routing paths and interconnection options, allowing flexible signal distribution across different device surfaces.

Inventive Principle:
Principle #1Segmentation

2Productivity

If geometric size is decreased for scaling, then production efficiency increases, but interconnection options are restricted

Engineering Contradiction:
Improveproduction efficiencyVSAvoidinterconnection options
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

As device geometric dimensions are scaled down to improve production efficiency, the patent compensates for reduced interconnection options by utilizing the third dimension (backside contacts). This vertical and bidirectional expansion of the interconnection architecture maintains routing flexibility despite planar dimension reductions.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Adaptability or versatility

If more interconnection options are provided, then signal routing flexibility improves, but device complexity increases

Engineering Contradiction:
Improveinterconnection optionsVSAvoiddevice structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The backside source/drain contacts serve multiple functions: they provide additional signal routing paths, enable alternative interconnection configurations, and can support both frontside and backside distributed interconnection structures. This multi-functionality increases interconnection options while managing device complexity through versatile contact utilization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250287642A1Semiconductor structure and method for forming the same
Publication Date: 2025.09.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250287642A1 patent drawing
  • US20250287642A1 patent drawing
  • US20250287642A1 patent drawing

AI summary

A semiconductor structure includes a first transistor and a second transistor over the first transistor. The first transistor includes first nanostructures spaced apart from each other in a Z-direction, and first second source/drain features attached to opposite sides of the first nanostructures in an X-direction. The second transistor includes second nanostructures over the first nanostructures and spaced apart from each other in the Z-direction; and third and fourth source/drain features, attached to opposite sides of the second nanostructures in the X-direction and vertically overlapping the first and second source/drain features, respectively. The semiconductor structure further includes a gate structure that is wrapped around the first nanostructures and the second nanostructures. The semiconductor structure further includes a first source/drain contact, extending through the third source/drain feature and partially extending into the first source/drain feature; and a second source/drain contact extending into the first source/drain feature.