Stacked CMOS Transistor Structure for Higher Density Scaling
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Solution Overview
Problem
As technology advances, the challenge of increasing transistor density in integrated semiconductor devices becomes more difficult due to physical and material limitations on dimension shrink, necessitating novel configurations.
Innovation Solution
The approach involves forming stacked device structures by separately fabricating n-type and p-type metal oxide semiconductor (MOS) transistors on respective substrates and then bonding them to create vertically stacked CMOS devices, thereby increasing transistor density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dimension shrink is used to increase transistor density, then transistor density increases, but physical and material limitations prevent further shrinkage
Solution Approach 1:
The patent transitions from two-dimensional planar transistor layouts to three-dimensional vertically stacked transistor structures. Multiple transistor layers are stacked above each other, utilizing the vertical dimension to increase transistor density without further shrinking horizontal dimensions. This dimensional transition allows continued scaling despite reaching physical limits of miniaturization.
2Quantity of substance
If n-type and p-type MOS transistors are placed side-by-side in the same horizontal plane, then CMOS functionality is achieved, but transistor density is reduced
Solution Approach 1:
The patent implements vertical stacking of n-type and p-type MOS transistor layers in the third dimension, rather than placing them side-by-side in the same horizontal plane. This vertical arrangement maintains CMOS functionality while significantly increasing transistor density by utilizing available vertical space above each substrate.
Solution Approach 2:
The patent separates the fabrication of n-type and p-type MOS transistors onto different substrates, processes each substrate independently to optimize transistor formation, and then bonds the substrates together. This segmentation allows specialized processing for each transistor type while achieving high-density integrated CMOS devices through subsequent substrate bonding.
Data Source
AI summary
A complementary metal oxide semiconductor (CMOS) device includes a transistor of a first type formed over a first substrate, and a transistor of a second type formed over a second substrate. The CMOS device is formed when the transistor of the first type formed on the first substrate is bonded to the transistor of the second type formed over the second substrate.