Stacked CMOS Memory Array Layout for Dense DRAM Integration
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Solution Overview
Problem
Microelectronic device designers face challenges in increasing integration density and performance while minimizing the size and complexity of control logic devices within memory devices, as processing conditions and quantities of control logic devices hinder reductions in size and improvements in performance, leading to reduced memory density.
Innovation Solution
A microelectronic device structure comprising a first CMOS region with control logic devices underlying a memory array and a second CMOS region vertically overlying the memory array, with oxide-to-oxide bonding between the regions, allowing for reduced electrical connection lengths and increased memory cell density, and featuring vertical stacks of memory cells with conductive pillars and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If control logic devices are increased in quantity and complexity to handle denser memory arrays, then memory array density can be improved, but the horizontal footprint and real estate consumption of the device increases
Solution Approach 1:
The patent transitions control logic devices from a two-dimensional planar arrangement to a three-dimensional vertical stacking architecture. Multiple control logic regions are stacked vertically above the memory array, allowing control logic functionality to be distributed across multiple vertical levels. This dimensional transition enables increased memory array density in the planar direction without proportionally increasing the horizontal footprint, as control logic occupies the vertical dimension instead.
2Area of stationary object
If control logic devices are reduced in size to decrease horizontal footprint, then device compactness is improved, but processing conditions and performance requirements cannot be met
Solution Approach 1:
By stacking control logic regions vertically, the patent maintains adequate processing performance through distributed control logic across multiple levels while reducing the horizontal footprint. Each vertical level can be optimized for specific processing conditions, and the vertical stacking allows sufficient space for interconnect structures and routing without compromising performance.
Solution Approach 2:
The control logic is segmented into multiple distinct regions distributed across different vertical levels. Each control logic region can be independently optimized for specific functions and processing conditions, allowing performance requirements to be met while reducing individual component sizes and overall horizontal footprint.
3Ease of manufacture
If control logic devices are arranged in traditional planar configurations, then routing and interconnect structures can be simplified, but memory density is reduced due to real estate consumption
Solution Approach 1:
The patent implements vertical stacking of control logic regions with corresponding interconnect structures that route signals vertically between levels. This three-dimensional arrangement increases memory density by removing control logic from the planar footprint, while routing complexity is managed through systematic vertical interconnect design rather than simplified planar routing.
Data Source
AI summary
A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.