Stacked CMOS Voltage Driver With Speed-Up Gate Discharge
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Solution Overview
Problem
Existing voltage drivers struggle to switch high voltages at high speeds, particularly in CMOS processes where standard devices operate slower than required for applications like feed-forward electro-optical circuits.
Innovation Solution
The development of CMOS voltage driver devices with stacked transistor devices in a cascode arrangement, supported by a speed-up circuit that discharges parasitic capacitances, allowing for higher voltage differences without damaging individual transistors and enabling faster operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If standard CMOS devices are used for high voltage switching, then the device can operate at standard voltages with good performance, but the switching speed becomes slower when handling high voltages
Solution Approach 1:
The patent divides the high voltage switching function into multiple standard-voltage CMOS transistors connected in series (stacked configuration). Each transistor handles a portion of the total voltage, allowing the system to switch high voltages while maintaining the speed characteristics of standard CMOS devices. The segmentation of voltage handling across multiple devices resolves the contradiction between speed and voltage capability.
Solution Approach 2:
The patent transitions from a single-transistor architecture to a multi-transistor stacked architecture, adding the dimension of series connection. This dimensional change in circuit topology allows the system to handle higher voltages by distributing the voltage stress across multiple devices while maintaining fast switching speeds through parallel gate control.
2Reliability
If laterally diffused MOSFETs (LDMOS) are used to tolerate high voltages, then the device can handle high voltages, but the switching speed deteriorates and performance worsens
Solution Approach 1:
Instead of using specialized LDMOS transistors that inherently suffer from slow switching, the patent segments the high voltage handling function across multiple standard CMOS transistors in series. This segmentation allows each transistor to operate within its optimal voltage range while maintaining fast switching speeds, avoiding the speed penalty of LDMOS devices.
Solution Approach 2:
The patent changes the operating parameters by keeping each transistor in the stack operated at standard voltages rather than exposing individual transistors to high voltages. This parameter change (operating voltage per device) allows standard CMOS transistors to maintain their fast switching characteristics while the series stack collectively handles high voltages.
3Reliability
If multiple transistor devices are stacked in series to support larger voltage differences, then the voltage handling capability increases, but the parasitic capacitances slow down the switching speed
Solution Approach 1:
The patent extracts and separately manages the parasitic capacitance problem by introducing dedicated speed-up circuits for each transistor in the stack. These circuits actively discharge the parasitic capacitances during switching transitions, removing the speed-limiting effect of capacitance accumulation in the stacked configuration.
Solution Approach 2:
The patent introduces speed-up circuits as intermediary components between the control signal and the transistor gates. These intermediary circuits actively manage the parasitic capacitances by providing discharge paths, mediating between the need for high voltage support and the requirement for fast switching by controlling the capacitance discharge timing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables voltage drivers to handle arbitrarily large voltage ranges while maintaining the speed and performance of standard voltage devices, effectively addressing the need for high-speed switching in high-voltage applications.
Implementation Method 1
The speed-up circuit is configured to speed-up operation of the driver circuit via the selective discharging of gate-source capacitances
Data Source
AI summary
A voltage driver is provided that includes a driver circuit, comprising (i) first positive channel transistor devices (PCTDs) coupled in series between a reference node and an output node; and (ii) first negative channel transistor devices (NCTDs) coupled in series between the output node and an electrical ground node. The voltage driver further includes a speed-up circuit comprising: (i) second NCTDs coupled to the first PCTDs, configured to discharge gate-source capacitances of the first PCTDs; and (ii) second PCTDs coupled to the first NCTDs, configured to discharge gate-source capacitances of the first NCTDs. The voltage driver further includes a gate voltage circuit coupled to the driver circuit that includes third NCTDs and third PCTDs to provide respective first and second gate voltages to each of a subset of the first PCTDs and a subset of the first NCTDs.