Stacked CMOS Dual Work Function Gates Without Partial Metal Recess
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in forming dual work function metal gates for stacked CMOS transistor structures is the difficulty in controlling the partial metal recess process, which can lead to degraded performance due to incomplete removal of the first work function metal layer.
Innovation Solution
A method for fabricating stacked CMOS transistor structures with dual work function metal gates that eliminates the need for partial metal recesses by embedding one metal gate structure within another, ensuring precise fabrication of dual work function metals for both transistors without the need for partial metal recess processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If partial metal recess process is used to form dual work function metal gates, then device performance can be optimized, but manufacturing precision deteriorates due to incomplete removal of the first work function metal layer
Solution Approach 1:
The gate structure is segmented into two distinct metal gate layers (first work function metal layer and second work function metal layer) that are formed separately and embedded within a shared gate structure. This segmentation allows each metal layer to be independently controlled and deposited, eliminating the need for partial metal recess processes while achieving dual work function optimization for both NFET and PFET devices.
Solution Approach 2:
The first work function metal layer is embedded within the shared gate structure, and the second work function metal layer is subsequently formed around or within the first layer. This nested configuration allows both metal gates to coexist in a shared gate structure without requiring removal of either layer, thereby maintaining manufacturing precision while achieving dual work function performance.
2Productivity
If stacked CMOS transistor structures are formed to increase transistor density, then integration density is improved, but device complexity increases due to difficulty in forming dual work function metal gates
Solution Approach 1:
The NFET and PFET gate structures are merged into a single shared gate structure that contains both first and second work function metal layers. This merging approach allows stacked CMOS transistor structures to achieve high integration density while simplifying the fabrication process, as the shared gate structure can be formed in a single continuous process rather than requiring separate complex processing for each transistor type.
Solution Approach 2:
The shared gate structure serves multiple functions simultaneously: it acts as the gate for both the NFET and PFET devices, provides electrical connection to both transistor types, and houses both work function metal layers. This multi-functionality reduces fabrication complexity while maintaining high transistor density in the stacked configuration.
Data Source
AI summary
A device comprises a stacked transistor structure, and a shared gate structure. The stacked transistor structure comprises a first transistor of a first type, and a second transistor of a second type which is opposite the first type, and disposed over the first transistor. The shared gate structure comprises a first metal gate structure of the first transistor, and a second metal gate structure of the second transistor. The second metal gate structure is embedded in the first metal gate structure.