CMOS Power Amplifier Bias Circuit for Accurate Gate Biasing
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Solution Overview
Problem
Designing gate bias circuits for RF power amplifiers with stacked CMOS transistors is challenging due to low bandwidth and large errors in common mode DC voltages, which affect the reliability and linearity of the power amplifiers.
Innovation Solution
A bias circuit with a feedback module and multiple bias modules, using operational amplifiers and cascoded current mirrors, provides precise control of gate voltages through direct sampling and feedback, ensuring accurate output common mode voltage and maximizing bandwidth by reducing the number of feedback loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple MOS transistors are stacked together to share high supply voltage, then high power output is achieved, but gate DC bias control becomes critical and bandwidth decreases
Solution Approach 1:
The patent divides the stacked transistor configuration into separate NMOS and PMOS stacks, with independent bias control circuits for each stack. This segmentation allows independent optimization of each stack's gate bias, improving overall bandwidth while maintaining the high voltage sharing capability needed for high power output.
Solution Approach 2:
The patent implements feedback circuits that monitor the common-mode voltages at the gates of the stacked transistors and adjust the bias voltages accordingly. This feedback mechanism ensures precise gate bias control despite the stacked configuration, preventing bandwidth degradation while enabling high power operation.
2Reliability
If stacked CMOS transistors are used with complementarily stacked NMOS and PMOS, then high power efficiency and linearity are achieved, but demanding requirements are imposed on DC gate bias control
Solution Approach 1:
The patent introduces common-mode voltage control circuits as intermediary elements that simplify the bias control problem. By controlling the common-mode voltages at the gates of the stacked transistors, the circuit automatically ensures proper biasing for both NMOS and PMOS stacks, reducing the complexity of direct gate bias control while maintaining high efficiency and linearity.
Solution Approach 2:
The bias control circuits are designed to simultaneously control multiple parameters (common-mode voltages, gate biases, current distribution) through a unified control mechanism. This multi-functional approach reduces the number of independent control requirements while achieving the demanding bias conditions needed for high efficiency and linearity.
3Strength
If traditional bias circuits are used with stacked transistors, then high supply voltage is withstood, but low bandwidth and memory effects occur
Solution Approach 1:
The patent employs dynamic bias control circuits that can rapidly adjust gate biases in response to signal variations. This dynamic control maintains the voltage withstanding capability of the stacked transistor configuration while eliminating the bandwidth limitations and memory effects of static traditional bias circuits.
Data Source
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AI summary
Bias circuits for CMOS power amplifiers are provided. The bias circuit includes a feedback module (21), a first bias module, and a second bias module. The feedback module (21) has a first input connected to a output common mode voltage, a second input connected to a reference voltage, and an output connected to gates of main amplification transistors in a first differential amplification module (31a); based on a difference between the output common mode voltage and the reference voltage, the feedback module (21) adjusts gate voltages of main amplification transistors until the output common mode voltage is equal to the reference voltage; the first bias module provides bias voltages for the first differential amplification module (31a); the second bias module provides bias voltages for a second differential amplification module (32a). The present disclosure adopts direct negative feedback and cascoded current mirrors, which realize accurate DC gate bias and accurate control of the output common mode voltage.