Stacked CMOS Latch Cross-Connections Through Vertical Gate Cuts
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Solution Overview
Problem
Forming cross-connections in stacked CMOS transistor pairs presents a challenge, especially at nodes beyond 5 nm, as existing methods are not effectively adapted for stacked structures despite ease in planar arrays.
Innovation Solution
The method involves forming lower dummy gates, wafer bonding for upper channels, creating openings between upper and lower dummy gates, replacing with metal gates, and forming gate cuts to connect upper and lower transistors across stacked pairs, enabling integrated device cross-connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If cross-connections are formed in planar transistor arrays, then latch circuit implementation is straightforward, but forming comparable cross-connections in stacked structures becomes complex and challenging
Solution Approach 1:
The patent transitions from planar (2D) transistor arrays to stacked (3D) structures by adding the vertical dimension. Cross-connections are formed between upper and lower transistor layers through vertical vias and interconnect structures, enabling latch circuits in a three-dimensional configuration that overcomes the limitations of planar scaling while maintaining manufacturing feasibility through adapted fabrication processes
2Productivity
If stacked transistor structures are implemented to increase density, then device integration is improved, but the ability to form cross-connections for latch circuits deteriorates
Solution Approach 1:
The stacked transistor structure is segmented into distinct upper and lower layers with separate gate controls. Cross-connections are established through carefully positioned vias that connect specific drain/source regions between layers, allowing independent control of each transistor while enabling latch functionality. This segmentation maintains high density while restoring the adaptability needed for latch circuit formation
Data Source
AI summary
A semiconductor device including a first pair of stacked transistors having a first upper transistor and a first lower transistor, a second pair of stacked transistors comprising a second upper transistor and a second lower transistor, and a first cross-connection between the first upper transistor and the second lower transistor.