Vertically Stacked CMOS Layout for Higher Gate Density
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Solution Overview
Problem
Conventional CMOS devices face challenges in scaling down due to difficulties in integrating NMOS and PMOS transistors, leading to inadequate device integration density and footprint efficiency.
Innovation Solution
Implementing vertically-stacked CMOS transistors with both frontside and backside power rails, where transistors at the bottom of the stack are powered by backside power rails and those at the top by frontside power rails, increasing the number of metal tracks and gate density, and utilizing GAA devices with horizontally-oriented multi-channel transistors like nanowire or nanosheet transistors for better gate control and reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional side-by-side CMOS structure is used, then device integration is achieved, but scaling down becomes difficult and footprint efficiency is inadequate
Solution Approach 1:
The patent transitions from a two-dimensional side-by-side arrangement to a three-dimensional vertically-stacked configuration. Multiple transistor layers are stacked along the vertical dimension, allowing more transistors to be integrated within the same planar footprint. This dimensional change enables continued scaling and improved integration density without proportionally increasing the chip area.
Solution Approach 2:
The patent implements nested structures where smaller components are positioned within or between larger structural elements. Specifically, charge pump circuits are integrated within the memory cell structure, and multiple transistor layers are nested vertically with shared source/drain regions, maximizing space utilization and reducing overall footprint.
2Area of stationary object
If vertically-stacked CMOS transistors are implemented, then footprint is reduced by 25-30%, but device complexity increases with multiple power rails and stacking layers
Solution Approach 1:
The patent merges multiple functions into shared structures. Common source/drain regions serve multiple transistors across different layers, reducing the total number of discrete components. Power rails are shared between adjacent memory cells and circuit blocks, and the charge pump circuit shares structural elements with the memory cell array, thereby reducing overall device complexity despite the vertical stacking.
Solution Approach 2:
The patent implements universal structures that perform multiple functions. The vertically-stacked transistor layers use common source/drain regions that serve both as source for upper transistors and drain for lower transistors. Power rails are designed to serve multiple circuit blocks simultaneously, and the charge pump circuit uses shared interconnect structures with the memory array, reducing the need for dedicated components for each function.
3Reliability
If GAA devices with horizontally-oriented multi-channel transistors are used, then gate control is improved and leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the channel into multiple horizontal nanowire or nanosheet channels within each vertical transistor stack. This segmentation provides multiple independent conduction paths that can be precisely controlled by the gate, improving gate control effectiveness. The segmented structure also allows for better isolation and reduced leakage between channels while maintaining manufacturability through standardized fabrication processes.
Data Source
AI summary
A semiconductor structure includes a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.