Stacked CMOS Gate Layout for High-Integration Reliability
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Solution Overview
Problem
Existing CMOS devices face challenges in achieving high integration and performance due to the limitations of stacking NMOSFET and PMOSFET transistors, which can lead to deterioration of the bottom transistor's performance during high-temperature processing.
Innovation Solution
A semiconductor device is designed with a stacked structure where a second metal-oxide semiconductor transistor is placed on top of a first semiconductor transistor, with the second gate stack overlapping the first gate stack by at least 90% in cross-section. This configuration uses low-temperature evaporation to form the second transistor without compromising the first transistor's performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If NMOSFET and PMOSFET transistors are stacked to improve integration, then the degree of integration is improved, but the bottom transistor's performance deteriorates due to high-temperature processing
Solution Approach 1:
The patent transitions from planar arrangement to vertical stacking of transistors, moving from two-dimensional to three-dimensional configuration. This dimensional change enables higher integration density while the selective formation of the second transistor only on exposed regions protects the bottom transistor from damage
Solution Approach 2:
The first transistor is formed completely before forming the second transistor. The gate electrode and gate dielectric of the first transistor are prepared in advance, and only the channel layer, source/drain electrodes, and interlayer insulator are selectively removed in specific regions before forming the second transistor, preventing damage to the already-formed first transistor
2Area of stationary object
If the second gate stack overlaps the first gate stack by at least 90% to achieve miniaturization, then the device area is reduced, but the manufacturing precision requirement increases
Solution Approach 1:
The second gate stack is positioned to overlap and nest within the horizontal footprint of the first gate stack, with the overlap ratio controlled at 90% or more. This nesting arrangement minimizes the total device area while the selective removal process provides natural alignment references that reduce manufacturing precision requirements
3Reliability
If low-temperature evaporation is used to form the second transistor to protect the first transistor, then the bottom transistor performance is maintained, but the manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: first transistor formation, selective removal of specific layers (channel layer, source/drain electrodes, interlayer insulator) in exposed regions, and second transistor formation. This segmentation allows low-temperature evaporation to be applied only where needed, protecting the first transistor while maintaining process feasibility
Data Source
AI summary
Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.