Stacked CMOS Image Sensor Layout for Global Shutter Pixels
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Solution Overview
Problem
Conventional image sensing structures suffer from image distortion due to charging effects, particularly in CMOS image sensors, and require improved pixel area efficiency as sensor sizes decrease.
Innovation Solution
The implementation of a solid-state CMOS image sensor array with global shutter capabilities, where charges are transferred from a photodiode to a transfer gate, and the integration of a row selector on an ASIC chip with an analog-to-digital converter (ADC) through pixel level hybrid bonding to reduce sensor/pixel areas and eliminate image distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If sensor device size is decreased, then device compactness is improved, but pixel area becomes insufficient
Solution Approach 1:
The patent divides the image sensor into two separate devices: a first device containing photodiodes for light reception and a second device containing pixel circuits for signal processing. This segmentation allows each device to be optimized independently, enabling smaller overall sensor size while maintaining adequate pixel area in the photodiode layer.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture where the first and second devices are bonded together vertically. This dimensional change enables independent optimization of photodiode area in the first device and circuit area in the second device, resolving the area-size contradiction.
2Ease of manufacture
If conventional CMOS image sensor structure is used, then manufacturing simplicity is maintained, but image distortion occurs due to charging effect
Solution Approach 1:
The patent extracts the pixel circuits from the photodiode layer and places them in a separate second device. This removal eliminates the charging effect interference that occurs in conventional integrated structures, as the photodiodes are no longer in direct contact with the pixel circuits that cause distortion.
Solution Approach 2:
The patent introduces a transfer gate mechanism as an intermediary between the photodiodes in the first device and the pixel circuits in the second device. This mediator enables controlled charge transfer while maintaining physical separation, thus eliminating direct charging effect interference while still allowing signal transmission.
3Device complexity
If pixel circuits are integrated with photodiodes in the same device, then device complexity is reduced, but image distortion due to charging effect occurs
Solution Approach 1:
The patent segments the image sensor into two distinct devices with separate functions: the first device dedicated to light reception and the second device dedicated to signal processing. This segmentation resolves the contradiction by physically separating the sources of image distortion from the photodiodes while maintaining functional integration through bonding.
Solution Approach 2:
The patent resolves the complexity-distortion contradiction by moving from horizontal integration to vertical stacking. The two devices are bonded together in the third dimension, maintaining functional integration while eliminating the harmful charging effects that occur in planar integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances pixel area efficiency, reduces image distortion by using global shutter capabilities, and enables immediate signal transfer, maintaining sensitivity in smaller camera devices.
Implementation Method 1
a photodiode adjacent to the top side of the second semiconductor device and configured to receive the light incident on the top side of the second semiconductor device
Data Source
AI summary
The image sensing structure includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes at least one first unit. The at least one first unit includes a plurality of first interconnects adjacent to the top side of the first semiconductor device, a row selector, and an analog-to-digital converter (ADC) connected to the row selectors. The second semiconductor device includes at least one second unit. The at least one second unit includes a photodiode facing the top side of the second semiconductor device. The photodiode is configured to receive the light incident on the top side of the second semiconductor device. The top side of the first semiconductor device is bonded to the bottom side of the second semiconductor device.