Stacked CMOS Image Sensor Chips for High Fill Factor
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Solution Overview
Problem
Backside Illumination (BSI) image sensor chips face limitations in quantum efficiency due to the space occupied by logic devices such as transfer gate transistors, reset transistors, and source followers, which reduce the fill factor and overall performance of the pixel units.
Innovation Solution
A stacked image sensor chip structure is implemented, where the image sensor chip is bonded to a read-out chip and a peripheral circuit chip, with logic devices like row selectors, source followers, and reset transistors moved out of the image sensor chip to improve fill factor and quantum efficiency, and reconfigured to reduce chip size and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If logic devices (transfer gate transistors, reset transistors, source followers, row selectors) are integrated in the same pixel unit as image sensors, then the pixel unit can be completed in a single chip formation process, but the fill factor is reduced and quantum efficiency is limited
Solution Approach 1:
The patent divides the pixel unit into two separate chips: the image sensor chip containing only the image sensor, and the read-out chip containing all logic devices (transfer gate transistors, reset transistors, source followers, row selectors). This segmentation allows the image sensor to occupy the maximum area on its chip, achieving high fill factor and quantum efficiency, while logic devices are properly formed on the read-out chip without area constraints from the image sensor.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration of all pixel unit components on a single chip to a three-dimensional stacked architecture where the image sensor chip and read-out chip are vertically bonded. This dimensional change enables both chips to be optimized for their respective functions without competing for the same planar space, resolving the fill factor limitation while maintaining manufacturing integration.
2Manufacturing precision
If logic devices are moved out of the image sensor chip to improve fill factor, then quantum efficiency is improved, but the device structure becomes more complex
Solution Approach 1:
By segmenting the pixel unit into two specialized chips, each chip can be independently optimized for its specific function. The image sensor chip focuses solely on photon detection with maximum fill factor, while the read-out chip handles all logic operations. This functional segmentation simplifies the design and manufacturing of each individual chip compared to integrating all functions in one complex chip.
Solution Approach 2:
The read-out chip is designed as a universal component that can be paired with different image sensor chip types (different wavelengths, different sensor configurations). This multi-functionality approach allows the complex logic circuitry to be standardized and reused across multiple product variants, reducing overall system complexity despite the stacked architecture.
3Adaptability or versatility
If all logic circuits are integrated in the image sensor chip, then the chip can be fully customized for different applications, but the manufacturing cycle time increases
Solution Approach 1:
The patent segments the pixel unit into reusable image sensor chip and read-out chip components. The read-out chip with its logic devices can be manufactured in advance and stored, while image sensor chips can be produced in batches. When customization is needed, pre-manufactured read-out chips can be quickly bonded to new image sensor chips, significantly reducing the manufacturing cycle time compared to producing fully integrated custom chips for each application.
Solution Approach 2:
The read-out chip containing complex logic circuits can be manufactured, tested, and prepared in advance as a standardized component. This preliminary action allows the time-consuming logic circuit fabrication to be completed beforehand, so that when customization is required, only the image sensor chip needs to be manufactured and then quickly assembled with the pre-prepared read-out chip, reducing overall manufacturing cycle time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the fill factor of pixel units, improves quantum efficiency, signal-to-noise ratio, and sensitivity, while allowing for customized peripheral circuits in a separate chip, enabling easier redesign for different applications and reducing manufacturing cycles.
Implementation Method 1
The image sensors in the BSI image sensor chips generate electrical signals in response to the stimulation of photons
Implementation Method 2
bonded through metal-to-metal bonding or a hybrid bonding including both the metal-to-metal bonding and the oxide-to-oxide bonding
Implementation Method 3
hybrid bonding including both the metal-to-metal bonding and the oxide-to-oxide bonding
Data Source
AI summary
A device includes an image sensor chip including an image sensor therein. A read-out chip is underlying and bonded to the image sensor chip. The read-out chip includes a logic device selected from the group consisting essentially of a reset transistor, a source follower, a row selector, and combinations thereof therein. The logic device and the image sensor are electrically coupled to each other, and are parts of a same pixel unit. A peripheral circuit chip is underlying and bonded to the read-out chip. The peripheral circuit chip includes a logic circuit, a through via penetrating through a semiconductor substrate of the peripheral circuit chip, and an electrical connector at a bottom surface of the peripheral circuit chip. The electrical connector is electrically coupled to the logic circuit in the peripheral circuit chip through the through via.