Stacked CMOS Image Sensor Vertical Transistor Pixel Design
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Solution Overview
Problem
The challenge is to reduce pixel size and improve sensitivity in CMOS image sensors while maintaining compatibility with existing technologies, as silicon-based multiplication sensors face difficulties in integration due to novel pixel structures and circuit configurations.
Innovation Solution
A solid-state image sensor design incorporating a photoelectric conversion unit, a read-out unit, a multiplication region, and a transfer unit that generates an intense electric field for avalanche effect-based charge multiplication, allowing for temporary storage and transfer of electric charge to convert it into a pixel signal, enabling size reduction and sensitivity enhancement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multiplication region is added to CMOS image sensors to improve sensitivity, then sensitivity is improved, but pixel size cannot be reduced due to additional structure requirements
Solution Approach 1:
The patent combines the multiplication region with the existing pixel structure, making the multiplication region share the same space as the photoelectric conversion unit and transistor. This merging approach allows sensitivity improvement through charge multiplication without adding separate multiplication sensor structures, thereby enabling pixel size reduction while maintaining the multiplication function.
Solution Approach 2:
The multiplication region is designed to serve multiple functions: it acts as both a charge storage region and a charge multiplication region. By generating intense electric fields within this region, the same structure performs both temporary charge storage and avalanche multiplication, eliminating the need for separate dedicated multiplication components and reducing overall pixel complexity.
2Productivity
If pixel size is reduced to increase pixel density, then productivity is improved, but sensitivity decreases due to insufficient PD region
Solution Approach 1:
The patent utilizes the depth dimension (vertical direction) to separate the photoelectric conversion unit and transistor, allowing the PD region to extend deeper into the substrate. This vertical extension increases the effective photoelectric conversion volume without increasing the planar pixel area, thereby maintaining sensitivity while enabling higher pixel density.
Solution Approach 2:
The patent changes the physical parameters of the multiplication region by generating intense electric fields through applied voltages. This creates avalanche multiplication effects that amplify the charge signals from small PD regions, effectively compensating for the reduced photoelectric conversion area in smaller pixels and maintaining sensitivity despite reduced pixel size.
3Reliability
If PD and transistor are separated in depth direction to maintain saturated electric charge amount, then sensitivity is maintained, but device complexity increases
Solution Approach 1:
The patent merges the multiplication region with the transistor structure, where the multiplication region is positioned to share space with the transistor. This integration allows the separation of PD and transistor in the depth direction to be achieved without proportionally increasing overall device complexity, as the multiplication function is incorporated into the existing transistor area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves a reduction in pixel size and enhances sensitivity, maintaining compatibility with CMOS image sensors and allowing for higher integration and efficient charge multiplication, even at low illuminance.
Implementation Method 1
a photoelectric conversion unit configured to convert light into electric charge by photoelectric conversion
Implementation Method 2
a step of generating an intense electric field region in the multiplication region to multiply electric charge by an avalanche effect
Data Source
AI summary
The present disclosure relates to a solid-state image sensor, driving method, and electronic apparatus, capable of achieving reduction in pixel size and sensitivity improvement. The solid-state image sensor includes a PD configured to convert light into electric charge by photoelectric conversion and to store the electric charge, a first transfer transistor configured to read out the electric charge stored in the photoelectric conversion unit, a multiplication region configured to store temporarily and multiply the electric charge read out through the read-out unit, and a second transfer transistor configured to transfer the electric charge stored in the multiplication region to a conversion unit configured to convert the electric charge into a pixel signal. Then, an intense electric field is generated in the multiplication region to multiply electric charge by the avalanche effect in transferring the electric charge from the multiplication region to an FD portion through the second transfer transistor. The present technology is applicable to, in one example, the stacked CMOS image sensors.